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base repository: hackndev/zinc
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head repository: gsnoff/zinc
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  • 14 commits
  • 25 files changed
  • 2 contributors

Commits on Oct 22, 2014

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  8. UART works!

    simias committed Oct 22, 2014
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Commits on Oct 23, 2014

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  2. Ported pin.rs to ioregs!

    simias committed Oct 23, 2014
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Commits on Oct 25, 2014

  1. Port Timer code to ioregs

    simias committed Oct 25, 2014
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  2. Remove .dir-locals.el

    simias committed Oct 25, 2014
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  3. Ported UART to ioregs

    simias committed Oct 25, 2014
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6 changes: 5 additions & 1 deletion Rakefile
Original file line number Diff line number Diff line change
@@ -179,6 +179,10 @@ when 'k20'
task :build_all => [:build_blink_k20, :build_blink_k20_isr]
when 'stm32f4'
task :build_all => [:build_blink_stm32f4]
else
when 'lpc17xx'
task :build_all => [:build_empty, :build_blink]
when 'tiva_c'
task :build_all => [:build_blink_tiva_c, :build_uart_tiva_c]
else
puts "I don't know what to build for this platform."
end
68 changes: 68 additions & 0 deletions apps/app_blink_tiva_c.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,68 @@
#![feature(phase)]
#![crate_type="staticlib"]
#![no_std]

extern crate core;
extern crate zinc;
#[phase(plugin)] extern crate macro_platformtree;

platformtree!(
tiva_c@mcu {
clock {
source = "MOSC";
/* Y2 16Mhz oscillator on launchpad board */
source_frequency = 16_000_000;
}

gpio {
PortF {
led1@1 { direction = "out"; }
led2@2 { direction = "out"; }
}
}

timer {
/* The mcu contain both 16/32bit and "wide" 32/64bit timers. */
timer@w0 {
/* prescale sysclk to 1Mhz since the wait code expects 1us
* granularity */
prescale = 80;
mode = "periodic";
}
}
}

os {
single_task {
loop = "run";
args {
timer = &timer;
led1 = &led1;
led2 = &led2;
}
}
}
)

pub fn run(args: &pt::run_args) {
use zinc::hal::pin::GPIO;
use zinc::hal::timer::Timer;

use core::option::{Some};

use zinc::hal::tiva_c::sysctl::clock::{MOSC, X16_0MHz, sysclk_configure};

sysclk_configure(MOSC, Some(X16_0MHz), true, Some(5));

loop {
args.led1.set_high();
args.led2.set_low();

args.timer.wait(1);

args.led1.set_low();
args.led2.set_high();

args.timer.wait(1);
}
}
84 changes: 84 additions & 0 deletions apps/app_uart_tiva_c.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,84 @@
#![feature(phase)]
#![crate_type="staticlib"]
#![no_std]

extern crate core;
extern crate zinc;
#[phase(plugin)] extern crate macro_platformtree;

platformtree!(
tiva_c@mcu {
clock {
source = "MOSC";
/* Y2 16Mhz oscillator on launchpad board */
source_frequency = 16_000_000;
}

timer {
/* The mcu contain both 16/32bit and "wide" 32/64bit timers. */
timer@w0 {
/* prescale sysclk to 1Mhz since the wait code expects 1us
* granularity */
prescale = 16;
mode = "periodic";
}
}


gpio {
PortA {
uart_rx@0 {
direction = "in";
function = 1;
}
uart_tx@1 {
direction = "in";
function = 1;
}
}
PortF {
txled@2 { direction = "out"; }
}
}

uart {
uart@0 {
mode = "115200,8n1";
}
}

}

os {
single_task {
loop = "run";
args {
timer = &timer;
uart = &uart;
txled = &txled;
uart_tx = &uart_tx;
}
}
}
)

fn run(args: &pt::run_args) {
use zinc::drivers::chario::CharIO;
use zinc::hal::timer::Timer;
use zinc::hal::pin::GPIO;

args.uart.puts("Hello, world\n");

let mut i = 0;
loop {
args.txled.set_high();
args.uart.puts("Waiting for ");
args.uart.puti(i);
args.uart.puts(" seconds...\n");

i += 1;
args.txled.set_low();

args.timer.wait(1);
}
}
2 changes: 2 additions & 0 deletions platforms.yml
Original file line number Diff line number Diff line change
@@ -6,3 +6,5 @@ stm32f4:
arch: cortex_m4
k20:
arch: cortex_m4
tiva_c:
arch: cortex_m4
2 changes: 2 additions & 0 deletions src/platformtree/builder/mcu.rs
Original file line number Diff line number Diff line change
@@ -17,6 +17,7 @@ use std::rc::Rc;
use syntax::ext::base::ExtCtxt;

use lpc17xx_pt;
use tiva_c_pt;
use node;

use super::Builder;
@@ -26,6 +27,7 @@ pub fn attach(builder: &mut Builder, cx: &mut ExtCtxt, node: Rc<node::Node>) {
Some(ref name) => {
match name.as_slice() {
"lpc17xx" => lpc17xx_pt::attach(builder, cx, node.clone()),
"tiva_c" => tiva_c_pt::attach(builder, cx, node.clone()),
_ => node.materializer.set(Some(fail_build_mcu)),
}
},
6 changes: 6 additions & 0 deletions src/platformtree/platformtree.rs
Original file line number Diff line number Diff line change
@@ -17,9 +17,14 @@
#![experimental]
#![feature(quote)]
#![feature(phase)]
#![crate_name="platformtree"]
#![crate_type="rlib"]

#[phase(plugin)]

extern crate regex_macros;
extern crate regex;
extern crate syntax;
#[cfg(test)] extern crate hamcrest;

@@ -28,6 +33,7 @@ pub mod node;
pub mod parser;

#[path="../zinc/hal/lpc17xx/platformtree.rs"] mod lpc17xx_pt;
#[path="../zinc/hal/tiva_c/platformtree.rs"] mod tiva_c_pt;
#[path="../zinc/drivers/drivers_pt.rs"] mod drivers_pt;

#[cfg(test)] mod test_helpers;
4 changes: 4 additions & 0 deletions src/zinc/hal/isr.rs
Original file line number Diff line number Diff line change
@@ -31,4 +31,8 @@ extern crate core;
#[cfg(mcu_k20)]
#[path="k20/isr.rs"] pub mod isr_k20;

#[cfg(mcu_tiva_c)]
#[path="tiva_c/isr.rs"] pub mod isr_tiva_c;


#[path="../util/lang_items.rs"] mod lang_items;
1 change: 1 addition & 0 deletions src/zinc/hal/lpc17xx/pin.rs
Original file line number Diff line number Diff line change
@@ -61,6 +61,7 @@ impl Pin {
port: port,
pin: pin_index,
};

pin.setup_regs(function, gpiodir);

pin
4 changes: 2 additions & 2 deletions src/zinc/hal/lpc17xx/pin_pt.rs
Original file line number Diff line number Diff line change
@@ -44,7 +44,7 @@ fn build_pin(builder: &mut Builder, cx: &mut ExtCtxt, node: Rc<node::Node>) {
0...4 => port_path,
other => {
cx.parse_sess().span_diagnostic.span_err(port_node.path_span,
format!("unknown port `{}`, allowed values: 0..4",
format!("unknown port `{}`, allowed values: 0...4",
other).as_slice());
return;
}
@@ -78,7 +78,7 @@ fn build_pin(builder: &mut Builder, cx: &mut ExtCtxt, node: Rc<node::Node>) {
0...31 => &node.path,
other => {
cx.parse_sess().span_diagnostic.span_err(node.path_span,
format!("unknown pin `{}`, allowed values: 0..31",
format!("unknown pin `{}`, allowed values: 0...31",
other).as_slice());
return;
}
1 change: 1 addition & 0 deletions src/zinc/hal/mod.rs
Original file line number Diff line number Diff line change
@@ -25,6 +25,7 @@ and each such struct has a `setup()` method that configures the hardware
pub mod lpc17xx;
pub mod stm32f4;
pub mod k20;
pub mod tiva_c;

mod cortex_common;
pub mod cortex_m3;
59 changes: 59 additions & 0 deletions src/zinc/hal/tiva_c/io.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,59 @@
//! Custom register access interface
use core::intrinsics::{volatile_load, volatile_store};

/// Hardware register interface
pub struct Reg {
/// Register address
addr: u32,
}

impl Reg {
/// create a new Reg from a 32bit register address
pub fn new(addr: u32) -> Reg {
Reg { addr: addr }
}

/// Write to a 32bit register
#[inline]
pub fn write32(&self, val: u32) {
unsafe {
let r = self.addr as *mut u32;
volatile_store(r, val);
}
}

/// Read from a 32bit register
#[inline]
pub fn read32(&self) -> u32 {
unsafe {
let r = self.addr as *const u32;
volatile_load(r)
}
}

/// Write single bit to a register using hardware bitbanding
#[inline]
pub fn bitband_write(&self, bit: u8, set: bool) {
/* bitband offset */
let mut bitband = (self.addr & 0xf0000000) | 0x02000000;

/* register offset */
bitband |= (self.addr & 0x00fffff) << 5;
/* bit offset */
bitband |= (bit as u32) << 2;

unsafe {
let r = bitband as *mut u32;
volatile_store(r, set as u32);
}
}
}

/// Hack to get a static 'ioreg' reference from a raw pointer to the register
/// base
pub fn get_reg_ref<T>(t: *const T) -> &'static T {
unsafe {
&*t
}
}
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