Basic pin control for tm4c123gh6pm. Can light up a LED!

apps/app_blink_tm4c123gh6pm.rs

@@ -4,10 +4,39 @@
 
 extern crate core;
 extern crate zinc;
+#[phase(plugin)] extern crate macro_platformtree;
+
+platformtree!(
+  tm4c123gh6pm@mcu {
+    clock {
+      source = "MOSC";
+      /* Y2 16Mhz oscillator on launchpad board */
+      source_frequency = 16_000_000;
+    }
+
+    gpio {
+        PortF {
+            led1@1 { direction = "out"; }
+            led2@2 { direction = "out"; }
+      }
+    }
+  }
+
+  os {
+    single_task {
+      loop = "run";
+      args {
+        led1 = &led1;
+        led2 = &led2;
+      }
+    }
+  }
+)
 
-#[no_mangle]
 #[no_split_stack]
-#[allow(unused_variable)]
-#[allow(dead_code)]
-pub unsafe fn main() {
+pub fn run(args: &pt::run_args) {
+    use zinc::hal::pin::GPIO;
+
+    args.led1.set_high();
+    args.led2.set_high();
 }

src/platformtree/builder/mcu.rs

@@ -17,6 +17,7 @@ use std::rc::Rc;
 use syntax::ext::base::ExtCtxt;
 
 use lpc17xx_pt;
+use tm4c123gh6pm_pt;
 use node;
 
 use super::Builder;
@@ -25,7 +26,8 @@ pub fn attach(builder: &mut Builder, cx: &mut ExtCtxt, node: Rc<node::Node>) {
   match node.name {
     Some(ref name) => {
       match name.as_slice() {
-        "lpc17xx" => lpc17xx_pt::attach(builder, cx, node.clone()),
+        "lpc17xx"      => lpc17xx_pt::attach(builder, cx, node.clone()),
+        "tm4c123gh6pm" => tm4c123gh6pm_pt::attach(builder, cx, node.clone()),
         _ => node.materializer.set(Some(fail_build_mcu)),
       }
     },

src/platformtree/platformtree.rs

@@ -28,6 +28,7 @@ pub mod node;
 pub mod parser;
 
 #[path="../zinc/hal/lpc17xx/platformtree.rs"] mod lpc17xx_pt;
+#[path="../zinc/hal/tm4c123gh6pm/platformtree.rs"] mod tm4c123gh6pm_pt;
 #[path="../zinc/drivers/drivers_pt.rs"] mod drivers_pt;
 
 #[cfg(test)] mod test_helpers;

src/zinc/hal/isr.rs

@@ -31,4 +31,8 @@ extern crate core;
 #[cfg(mcu_k20)]
 #[path="k20/isr.rs"] pub mod isr_k20;
 
+#[cfg(mcu_tm4c123gh6pm)]
+#[path="tm4c123gh6pm/isr.rs"] pub mod isr_tm4c123gh6pm;
+
+
 #[path="../util/lang_items.rs"] mod lang_items;

src/zinc/hal/lpc17xx/pin.rs

@@ -61,6 +61,7 @@ impl Pin {
       port: port,
       pin: pin_index,
     };
+
     pin.setup_regs(function, gpiodir);
 
     pin

src/zinc/hal/lpc17xx/pin_pt.rs

@@ -44,7 +44,7 @@ fn build_pin(builder: &mut Builder, cx: &mut ExtCtxt, node: Rc<node::Node>) {
     0...4 => port_path,
     other => {
       cx.parse_sess().span_diagnostic.span_err(port_node.path_span,
-          format!("unknown port `{}`, allowed values: 0..4",
+          format!("unknown port `{}`, allowed values: 0...4",
               other).as_slice());
       return;
     }
@@ -78,7 +78,7 @@ fn build_pin(builder: &mut Builder, cx: &mut ExtCtxt, node: Rc<node::Node>) {
     0...31 => &node.path,
     other  => {
       cx.parse_sess().span_diagnostic.span_err(node.path_span,
-          format!("unknown pin `{}`, allowed values: 0..31",
+          format!("unknown pin `{}`, allowed values: 0...31",
               other).as_slice());
       return;
     }

src/zinc/hal/mod.rs

@@ -25,6 +25,7 @@ and each such struct has a `setup()` method that configures the hardware
 pub mod lpc17xx;
 pub mod stm32f4;
 pub mod k20;
+pub mod tm4c123gh6pm;
 
 mod cortex_common;
 pub mod cortex_m3;

src/zinc/hal/tm4c123gh6pm/io.rs

@@ -0,0 +1,52 @@
+//! Custom register access interface
+
+use util::volatile_cell::VolatileCell;
+use core::intrinsics::{volatile_load, volatile_store};
+
+/// Hardware register interface
+pub struct Reg {
+  /// Register address
+  addr: u32,
+}
+
+impl Reg {
+  /// create a new Reg from a 32bit register address
+  pub fn new(addr: u32) -> Reg {
+    Reg { addr: addr }
+  }
+
+  /// Write to a 32bit register
+  #[inline]
+  pub fn write32(&self, val: u32) {
+    unsafe {
+      let r = self.addr as *mut u32;
+      volatile_store(r, val);
+    }
+  }
+
+  /// Read from a 32bit register
+  #[inline]
+  pub fn read32(&self) -> u32 {
+    unsafe {
+      let r = self.addr as *const u32;
+      volatile_load(r)
+    }
+  }
+
+  /// Write single bit to a register using hardware bitbanding
+  #[inline]
+  pub fn bitband_write(&self, bit: u8, set: bool) {
+    /* bitband offset */
+    let mut bitband = (self.addr & 0xf0000000) | 0x02000000;
+
+    /* register offset */
+    bitband |= (self.addr & 0x00fffff) << 5;
+    /* bit offset */
+    bitband |= (bit as u32) << 2;
+
+    unsafe {
+      let r = bitband as *mut u32;
+      volatile_store(r, set as u32);
+    }
+  }
+}

src/zinc/hal/tm4c123gh6pm/isr.rs

@@ -0,0 +1,147 @@
+use core::option::{Option, None};
+
+static ISRCount: uint = 139;
+
+#[link_section=".isr_vector_nvic"]
+#[no_mangle]
+pub static NVIC_VECTOR: [Option<unsafe extern fn()>, ..ISRCount] = [
+    None,                      // GPIO Port A
+    None,                      // GPIO Port B
+    None,                      // GPIO Port C
+    None,                      // GPIO Port D
+    None,                      // GPIO Port E
+    None,                      // UART0 Rx and Tx
+    None,                      // UART1 Rx and Tx
+    None,                      // SSI0 Rx and Tx
+    None,                      // I2C0 Master and Slave
+    None,                      // PWM Fault
+    None,                      // PWM Generator 0
+    None,                      // PWM Generator 1
+    None,                      // PWM Generator 2
+    None,                      // Quadrature Encoder 0
+    None,                      // ADC Sequence 0
+    None,                      // ADC Sequence 1
+    None,                      // ADC Sequence 2
+    None,                      // ADC Sequence 3
+    None,                      // Watchdog timer
+    None,                      // Timer 0 subtimer A
+    None,                      // Timer 0 subtimer B
+    None,                      // Timer 1 subtimer A
+    None,                      // Timer 1 subtimer B
+    None,                      // Timer 2 subtimer A
+    None,                      // Timer 2 subtimer B
+    None,                      // Analog Comparator 0
+    None,                      // Analog Comparator 1
+    None,                      // Analog Comparator 2
+    None,                      // System Control (PLL, OSC, BO)
+    None,                      // FLASH Control
+    None,                      // GPIO Port F
+    None,                      // GPIO Port G
+    None,                      // GPIO Port H
+    None,                      // UART2 Rx and Tx
+    None,                      // SSI1 Rx and Tx
+    None,                      // Timer 3 subtimer A
+    None,                      // Timer 3 subtimer B
+    None,                      // I2C1 Master and Slave
+    None,                      // Quadrature Encoder 1
+    None,                      // CAN0
+    None,                      // CAN1
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Hibernate
+    None,                      // USB0
+    None,                      // PWM Generator 3
+    None,                      // uDMA Software Transfer
+    None,                      // uDMA Error
+    None,                      // ADC1 Sequence 0
+    None,                      // ADC1 Sequence 1
+    None,                      // ADC1 Sequence 2
+    None,                      // ADC1 Sequence 3
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // GPIO Port J
+    None,                      // GPIO Port K
+    None,                      // GPIO Port L
+    None,                      // SSI2 Rx and Tx
+    None,                      // SSI3 Rx and Tx
+    None,                      // UART3 Rx and Tx
+    None,                      // UART4 Rx and Tx
+    None,                      // UART5 Rx and Tx
+    None,                      // UART6 Rx and Tx
+    None,                      // UART7 Rx and Tx
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // I2C2 Master and Slave
+    None,                      // I2C3 Master and Slave
+    None,                      // Timer 4 subtimer A
+    None,                      // Timer 4 subtimer B
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // Timer 5 subtimer A
+    None,                      // Timer 5 subtimer B
+    None,                      // Wide Timer 0 subtimer A
+    None,                      // Wide Timer 0 subtimer B
+    None,                      // Wide Timer 1 subtimer A
+    None,                      // Wide Timer 1 subtimer B
+    None,                      // Wide Timer 2 subtimer A
+    None,                      // Wide Timer 2 subtimer B
+    None,                      // Wide Timer 3 subtimer A
+    None,                      // Wide Timer 3 subtimer B
+    None,                      // Wide Timer 4 subtimer A
+    None,                      // Wide Timer 4 subtimer B
+    None,                      // Wide Timer 5 subtimer A
+    None,                      // Wide Timer 5 subtimer B
+    None,                      // FPU
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // I2C4 Master and Slave
+    None,                      // I2C5 Master and Slave
+    None,                      // GPIO Port M
+    None,                      // GPIO Port N
+    None,                      // Quadrature Encoder 2
+    None,                      // Reserved
+    None,                      // Reserved
+    None,                      // GPIO Port P (Summary or P0)
+    None,                      // GPIO Port P1
+    None,                      // GPIO Port P2
+    None,                      // GPIO Port P3
+    None,                      // GPIO Port P4
+    None,                      // GPIO Port P5
+    None,                      // GPIO Port P6
+    None,                      // GPIO Port P7
+    None,                      // GPIO Port Q (Summary or Q0)
+    None,                      // GPIO Port Q1
+    None,                      // GPIO Port Q2
+    None,                      // GPIO Port Q3
+    None,                      // GPIO Port Q4
+    None,                      // GPIO Port Q5
+    None,                      // GPIO Port Q6
+    None,                      // GPIO Port Q7
+    None,                      // GPIO Port R
+    None,                      // GPIO Port S
+    None,                      // PWM 1 Generator 0
+    None,                      // PWM 1 Generator 1
+    None,                      // PWM 1 Generator 2
+    None,                      // PWM 1 Generator 3
+    None,                      // PWM 1 Fault*/
+];

src/zinc/hal/tm4c123gh6pm/layout.ld

@@ -1,4 +1,3 @@
-__STACK_BASE  = 0x10002000;
 _boot_checksum = 0; /* TODO(farcaller): extract this to lpc code only */
 _data_load = LOADADDR(.data);
 
@@ -12,6 +11,8 @@ MEMORY
     ram(WAIL) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32KB SRAM */
 }
 
+__STACK_BASE  = ORIGIN(ram) + LENGTH(ram);
+
 REGION_ALIAS("vectors", rom);
 
 INCLUDE ./src/zinc/hal/layout_common.ld

src/zinc/hal/tm4c123gh6pm/mod.rs

@@ -0,0 +1,8 @@
+//! HAL for TI TM4C123GH6PM
+//! This MCU is used on the TI stellaris and Tiva C launchpad development boards.
+
+pub mod io;
+pub mod sysctl;
+pub mod pin;
+
+#[path="../../util/ioreg.rs"] mod util;