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fixing segmentation print
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elbiazo committed Nov 19, 2023
1 parent d57fb1f commit 1a77405
Showing 1 changed file with 11 additions and 26 deletions.
37 changes: 11 additions & 26 deletions src/segmentation.rs
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,16 @@ impl SegmentSelector {
self.bits >> 3
}

/// Returns the requested privilege level of the selector.
pub fn rpl(&self) -> u16 {
self.bits & 0b11
}

/// Returns the table indicator (TI) bit.
pub fn ti(&self) -> u16 {
(self.bits >> 2) & 1
}

/// Make a new segment selector from a untyped u16 value.
pub const fn from_raw(bits: u16) -> SegmentSelector {
SegmentSelector { bits }
Expand All @@ -52,37 +62,12 @@ impl SegmentSelector {

impl fmt::Display for SegmentSelector {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
let r0 = match self.contains(SegmentSelector::RPL_0) {
false => "",
true => "Ring 0 segment selector.",
};
let r1 = match self.contains(SegmentSelector::RPL_1) {
false => "",
true => "Ring 1 segment selector.",
};
let r2 = match self.contains(SegmentSelector::RPL_2) {
false => "",
true => "Ring 2 segment selector.",
};
let r3 = match self.contains(SegmentSelector::RPL_3) {
false => "",
true => "Ring 3 segment selector.",
};
let tbl = match self.contains(SegmentSelector::TI_LDT) {
false => "GDT Table",
true => "LDT Table",
};

write!(
f,
"Index {} in {}, {}{}{}{}",
self.bits >> 3,
tbl,
r0,
r1,
r2,
r3
)
write!(f, "Index {} in {}, RPL = {}", self.index(), tbl, self.rpl())
}
}

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