Project is a memory cache simulator that traces the behaviour of the memory cache given the the cache information including: memory cache size (S), line size (L), and number of cycles to access memory (clk) ● Input is divided into 2 text files: ○ First one is: “input.txt” which includes: memory cache size (S), line size (L), and number of cycles to access memory (clk) ○ Second one is: “Memory Addresses.txt” for user to input sequence of 20 memory addresses in bytes ● The program traces and stores no. of accesses and no. of hits/misses, it displays the cache index alongside the valid bit and tag for each index. The hit/miss ratio is calculated as well as Average Memory Access Time (AMAT) value using the value of 100 clock cycles provided in the project description.
Created this project for the following course: CSCE230302 - Comp Org. and Assmbly Lang Prog in Fall 2022 at AUC.