simd_op_check failures for arm64 at recent top-of-tree LLVM

[steven-johnson]

Looks like recent LLVM changes have broken xtn usage; a git bisect locally suggests the culprit is:

65033ef9e8a6ecf7c2ad80c4e3e0c339b44e61b4 is the first bad commit
commit 65033ef9e8a6ecf7c2ad80c4e3e0c339b44e61b4
Author: Alexandros Lamprineas <alexandros.lamprineas@arm.com>
Date:   Tue Dec 14 11:28:22 2021 +0000

    [AArch64] Add a tablegen pattern for UZP1.

    Converts concat_vectors(V64 (trunc V128), V64 (trunc V128)), which
    would otherwise be lowered as xtn followed by xtn2, to uzp1.

    Differential Revision: https://reviews.llvm.org/D115435

 llvm/lib/Target/AArch64/AArch64InstrInfo.td        |  10 ++
 llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll   |   5 +-
 .../AArch64/concat_vector-truncate-combine.ll      |  46 +++++-
 .../CodeGen/AArch64/dag-combine-trunc-build-vec.ll |   3 +-
 llvm/test/CodeGen/AArch64/fcvt_combine.ll          |  72 +++++-----
 llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll  |  36 +++--
 llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll      | 160 ++++++++++-----------
 llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll     | 120 ++++++++--------
 llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll     | 124 ++++++++--------
 llvm/test/CodeGen/AArch64/neon-truncstore.ll       |  57 +++-----
 10 files changed, 323 insertions(+), 310 deletions(-)

[dsharletg]

Sounds like this might actually have been an optimization that simd_op_check is just brittle with respect to?

[steven-johnson]

Sounds like this might actually have been an optimization that simd_op_check is just brittle with respect to?

yep, fix on the way shortly