Add support for generating LLVM vector predication intrinsics. #7111
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added 17 commits
September 16, 2022 19:27
useful for RISC V, but it may be a simpler, better optimized path, for Halide vector operations in general. Add support for a maximum vector size that might be larger than the native vector size. RISC V vector LMUL support is an example of an architecture supporting this.
promotion contexts.
vector predication intrinsics.
improving the calling convention and naming of the new routines to generate the intrinsics.
steven-johnson
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Oct 21, 2022
abadams
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Oct 22, 2022
added 5 commits
October 24, 2022 18:06
caveperson programmer habits die hard. Improve comments.
concatenation into one line.
Change TODO(zalman) to TODO(zvookin) uniformly. Few other cleanups.
strided load for dense case. Add some comments.
ardier
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Mar 3, 2024
…e#7111) Add support for generating llvm.vp.* intrinsics. This is particularly useful for RISC V, but it may be a simpler, better optimized path, for Halide vector operations in general. Add support for a maximum vector size that might be larger than the native vector size. RISC V vector LMUL support is an example of an architecture supporting this.
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LLVM now has intrinsics for length bounded, predicated, vector operations. These are a generalization of the current vector IR LLVM has long had and will likely become the preferred way to generate pretty much all vector code in the future. (With appropriately restricted arguments to target existing fixed width SIMD instruction sets.)
Code has been tested in the riscv_update branch and will be used by the RISC V backend. PR has been separated out to make for a smaller, easier to review PR.
This required adding some helper methods to CodeGen_LLVM as the intrinsics have specific type mangling and argument pattterns that can be handled in common code.