Use VectorReverse to reverse scalable vector in LLVM #8884
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| Value *CodeGen_LLVM::reverse_vector(llvm::Value *vec) { | ||
| if (effective_vscale > 0) { |
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I believe this will affect RISC V as well and thus needs to be validated there. Is there test coverage for this?
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correctness_predicated_store_load
correctness_vector_math
cover this route at least on aarch64 host.
Unfortunately, I don't have a setup to test RISCV host. It would be good if it is tested on CI.
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I've made it ARM only for now. So, I suppose RISC V should not be affected.
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Actually, if you don't mind, please go ahead and put it back to being generic. I tested with and without the original change to generate code for RISC V and while the llvm.vector.reverse intrinsic shows up in the LLVM IR with the PR, and doea not without it, there is no difference in the generated RISC V assembly. (And it does compile correctly, at least with recent LLVM.) Of course I only looked at a simple test case and didn't run anything on real hardware, but I think this is enough diligence to say this change is a good one.
I'll go ahead and approve and merge after the change back, or another comment on this if you'd rather not for some reason.
LLVM VectorReverse could be used commonly, but for now we use it only in CodeGen_ARM until tested.
This reverts commit 7fd00b6 because the original change has been tested with RISCV target according to the PR comments.
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Failures are unrelated (WebGPU API nonsense and a failing arm32 LLVM build) |
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