Use Provided muxes test (#2)

* add provided muxes test

* conform to test file

* provided test works for our muxes

src/components/Makefile

@@ -20,7 +20,10 @@ test_sample : tests/test_sample.sv src/sample*.sv
 	${IVERILOG} $^ -o $@.bin && ${VVP} $@.bin ${VVP_POST}
 
 # Test mux
-test_mux : tests/test_mux.sv src/muxes/*.sv
+test_muxes_our : tests/our/test_muxes.sv src/muxes/*.sv
 	${IVERILOG} $^ -o $@.bin && ${VVP} $@.bin ${VVP_POST}
 
-all: test_sample test_mux
+test_muxes_provided : tests/provided/test_muxes.sv src/muxes/*.sv
+	${IVERILOG} $^ -o $@.bin && ${VVP} $@.bin ${VVP_POST}
+
+all: test_sample test_muxes_our test_muxes_provided

src/components/src/muxes/mux16.sv

@@ -1,23 +1,23 @@
 
 /* Design of 16-1 mux using binary module pattern */
-module mux16(in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8, in_9, in_10, in_11, in_12, in_13, in_14, in_15, s, out);
+module mux16(in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, s, out);
 
 
     parameter  N = 32;
 
     /* ----- Inputs  ----- */
-    input wire [N-1:0] in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8, in_9, in_10, in_11, in_12, in_13, in_14, in_15;
+    input wire [N-1:0] in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15;
     input wire [3:0] s;
 
     /* ----- Outputs  ----- */
     output logic [N-1:0] out;
 
     /* -----  Submodules -----  */ 
     logic [N-1:0] block_1_out ;
-    mux8 block_1(in_0, in_2, in_4, in_6, in_8, in_10, in_12, in_14, s[3:1], block_1_out);
+    mux8 block_1(in0, in2, in4, in6, in8, in10, in12, in14, s[3:1], block_1_out);
 
     logic [N-1:0] block_2_out ;
-    mux8 block_2(in_1, in_3, in_5, in_7, in_9, in_11, in_13, in_15, s[3:1], block_2_out);
+    mux8 block_2(in1, in3, in5, in7, in9, in11, in13, in15, s[3:1], block_2_out);
 
     mux2 block_3(block_1_out, block_2_out, s[0], out);
 

src/components/src/muxes/mux2.sv

@@ -1,17 +1,17 @@
 
-module mux2(in_0, in_1, s, out);
+module mux2(in0, in1, s, out);
 
     parameter  N = 32;
 
     /* ----- Inputs  ----- */
-    input wire [N-1:0] in_0, in_1; 
+    input wire [N-1:0] in0, in1; 
     input wire s;
 
     /* ----- Outputs  ----- */
     output logic [N-1:0] out;
 
     /* ----- Design  ----- */
-    assign out = s ? in_1 : in_0;
+    assign out = s ? in1 : in0;
 
 
 endmodule

src/components/src/muxes/mux32.sv

@@ -1,23 +1,23 @@
 
 /* Design of 32-1 mux using binary module pattern */
-module mux32(in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8, in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16, in_17, in_18, in_19, in_20, in_21, in_22, in_23, in_24, in_25, in_26, in_27, in_28, in_29, in_30, in_31, s, out);
+module mux32(in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, in16, in17, in18, in19, in20, in21, in22, in23, in24, in25, in26, in27, in28, in29, in30, in31, s, out);
 
 
     parameter  N = 32;
 
     /* ----- Inputs  ----- */
-    input wire [N-1:0] in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8, in_9, in_10, in_11, in_12, in_13, in_14, in_15, in_16, in_17, in_18, in_19, in_20, in_21, in_22, in_23, in_24, in_25, in_26, in_27, in_28, in_29, in_30, in_31;
+    input wire [N-1:0] in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, in16, in17, in18, in19, in20, in21, in22, in23, in24, in25, in26, in27, in28, in29, in30, in31;
     input wire [4:0] s;
 
     /* ----- Outputs  ----- */
     output logic [N-1:0] out;
 
     /* -----  Submodules -----  */ 
     logic [N-1:0] block_1_out ;
-    mux16 block_1(in_0, in_2, in_4, in_6, in_8, in_10, in_12, in_14, in_16, in_18, in_20, in_22, in_24, in_26, in_28, in_30, s[4:1], block_1_out);
+    mux16 block_1(in0, in2, in4, in6, in8, in10, in12, in14, in16, in18, in20, in22, in24, in26, in28, in30, s[4:1], block_1_out);
 
     logic [N-1:0] block_2_out ;
-    mux16 block_2(in_1, in_3, in_5, in_7, in_9, in_11, in_13, in_15, in_17, in_19, in_21, in_23, in_25, in_27, in_29, in_31, s[4:1], block_2_out);
+    mux16 block_2(in1, in3, in5, in7, in9, in11, in13, in15, in17, in19, in21, in23, in25, in27, in29, in31, s[4:1], block_2_out);
 
     mux2 block_3(block_1_out, block_2_out, s[0], out);
 

src/components/src/muxes/mux4.sv

@@ -1,22 +1,22 @@
 
 /* Design of 4-1 mux using binary module pattern */
-module mux4(in_0, in_1, in_2, in_3, s, out);
+module mux4(in0, in1, in2, in3, s, out);
 
     parameter  N = 32;
 
     /* ----- Inputs  ----- */
-    input wire [N-1:0] in_0, in_1, in_2, in_3;
+    input wire [N-1:0] in0, in1, in2, in3;
     input wire [1:0] s;
 
     /* ----- Outputs  ----- */
     output logic [N-1:0] out;
 
     /* -----  Submodules -----  */ 
     logic [N-1:0] block_1_out ;
-    mux2 block_1(in_0, in_2, s[1], block_1_out);
+    mux2 block_1(in0, in2, s[1], block_1_out);
 
     logic [N-1:0] block_2_out ;
-    mux2 block_2(in_1, in_3, s[1], block_2_out);
+    mux2 block_2(in1, in3, s[1], block_2_out);
 
     logic [N-1:0] block_3_out ;
     mux2 block_3(block_1_out, block_2_out, s[0], out);

src/components/src/muxes/mux8.sv

@@ -1,23 +1,23 @@
 
 /* Design of 8-1 mux using binary module pattern */
-module mux8(in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, s, out);
+module mux8(in0, in1, in2, in3, in4, in5, in6, in7, s, out);
 
 
     parameter  N = 32;
 
     /* ----- Inputs  ----- */
-    input wire [N-1:0] in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7;
+    input wire [N-1:0] in0, in1, in2, in3, in4, in5, in6, in7;
     input wire [2:0] s;
 
     /* ----- Outputs  ----- */
     output logic [N-1:0] out;
 
     /* -----  Submodules -----  */ 
     logic [N-1:0] block_1_out ;
-    mux4 block_1(in_0, in_2, in_4, in_6, s[2:1], block_1_out);
+    mux4 block_1(in0, in2, in4, in6, s[2:1], block_1_out);
 
     logic [N-1:0] block_2_out ;
-    mux4 block_2(in_1, in_3, in_5, in_7, s[2:1], block_2_out);
+    mux4 block_2(in1, in3, in5, in7, s[2:1], block_2_out);
 
     mux2 block_3(block_1_out, block_2_out, s[0], out );
 

src/components/tests/provided/test_muxes.sv

@@ -0,0 +1,147 @@
+`default_nettype none
+`timescale 1ns/1ps
+
+module test_muxes;
+// Testbench for muxes. Fixes inputs at unique values, then prints the output of each mux so you can compare.
+
+parameter N = 32;
+
+// python: print(", ".join([f"in{i}" for i in range(32)]))
+logic [N-1:0] in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11, in12, in13, in14, in15, in16, in17, in18, in19, in20, in21, in22, in23, in24, in25, in26, in27, in28, in29, in30, in31;
+wire [N-1:0] out2, out4, out8, out16, out32;
+logic [4:0] s;
+
+mux2 #(.N(N)) MUX2 (
+  .in0(in0),
+  .in1(in1),
+  .s(s[0]),
+  .out(out2)
+);
+
+mux4 #(.N(N)) MUX4 (
+  .in0(in0),
+  .in1(in1),
+  .in2(in2),
+  .in3(in3),
+  .s(s[1:0]),
+  .out(out4)
+);
+
+mux8 #(.N(N)) MUX8 (
+  .in0(in0),
+  .in1(in1),
+  .in2(in2),
+  .in3(in3),
+  .in4(in4),
+  .in5(in5),
+  .in6(in6),
+  .in7(in7),
+  .s(s[2:0]),
+  .out(out8)
+);
+
+mux16 #(.N(N)) MUX16 (
+  .in0(in0),
+  .in1(in1),
+  .in2(in2),
+  .in3(in3),
+  .in4(in4),
+  .in5(in5),
+  .in6(in6),
+  .in7(in7),
+  .in8(in8),
+  .in9(in9),
+  .in10(in10),
+  .in11(in11),
+  .in12(in12),
+  .in13(in13),
+  .in14(in14),
+  .in15(in15),
+  .s(s[3:0]),
+  .out(out16)
+);
+
+mux32 #(.N(N)) MUX32 (
+  .in0(in0),
+  .in1(in1),
+  .in2(in2),
+  .in3(in3),
+  .in4(in4),
+  .in5(in5),
+  .in6(in6),
+  .in7(in7),
+  .in8(in8),
+  .in9(in9),
+  .in10(in10),
+  .in11(in11),
+  .in12(in12),
+  .in13(in13),
+  .in14(in14),
+  .in15(in15),
+  .in16(in16),
+  .in17(in17),
+  .in18(in18),
+  .in19(in19),
+  .in20(in20),
+  .in21(in21),
+  .in22(in22),
+  .in23(in23),
+  .in24(in24),
+  .in25(in25),
+  .in26(in26),
+  .in27(in27),
+  .in28(in28),
+  .in29(in29),
+  .in30(in30),
+  .in31(in31),
+  .s(s),
+  .out(out32)
+);
+
+initial begin
+  $dumpfile("muxes.fst");
+  $dumpvars;
+  // python: print("\n".join([f"in{i} = {(i+1)**2};" for i in range(32)]))
+  in0 = 1;
+  in1 = 4;
+  in2 = 9;
+  in3 = 16;
+  in4 = 25;
+  in5 = 36;
+  in6 = 49;
+  in7 = 64;
+  in8 = 81;
+  in9 = 100;
+  in10 = 121;
+  in11 = 144;
+  in12 = 169;
+  in13 = 196;
+  in14 = 225;
+  in15 = 256;
+  in16 = 289;
+  in17 = 324;
+  in18 = 361;
+  in19 = 400;
+  in20 = 441;
+  in21 = 484;
+  in22 = 529;
+  in23 = 576;
+  in24 = 625;
+  in25 = 676;
+  in26 = 729;
+  in27 = 784;
+  in28 = 841;
+  in29 = 900;
+  in30 = 961;
+  in31 = 1024;
+  $display("%2s | %5s | %5s | %5s | %5s | %5s", "s", "mux2", "mux4", "mux8", "mux16", "mux32");
+  for(integer i=0; i< 32; i = i + 1) begin
+    s = i[4:0];
+    #10;
+    $display("%2d | %5d | %5d | %5d | %5d | %5d", s, out2, out4, out8, out16, out32);
+  end
+
+  $finish;
+end
+
+endmodule