4-1 mux with binary design pattern

src/components/mux_2_1.sv

@@ -13,7 +13,7 @@ module mux_2_1(input_1, input_2, select, mux_output);
     output logic [N-1:0] mux_output;
 
     /* ----- Design  ----- */
-    assign mux_output = select ? input_1 : input_2;
+    assign mux_output = select ? input_2 : input_1;
 
 
 endmodule

src/components/mux_4_1.sv

@@ -0,0 +1,24 @@
+
+/* Design of 4-1 mux using binary module pattern */
+module mux_4_1(input_1, input_2, input_3, input_4, select, mux_output);
+
+    parameter  N = 32;
+
+    /* ----- Inputs  ----- */
+    input wire [N-1:0] input_1, input_2, input_3, input_4; 
+    input wire [1:0] select;
+
+    /* ----- Outputs  ----- */
+    output logic [N-1:0] mux_output;
+
+    /* -----  Submodules -----  */ 
+    logic [N-1:0] block_1_out ;
+    mux_2_1 block_1(.input_1(input_1), .input_2(input_3), .select(select[1]), .mux_output(block_1_out) );
+
+    logic [N-1:0] block_2_out ;
+    mux_2_1 block_2(.input_1(input_2), .input_2(input_4), .select(select[1]), .mux_output(block_2_out) );
+
+    logic [N-1:0] block_3_out ;
+    mux_2_1 block_3(.input_1(block_1_out), .input_2(block_2_out), .select(select[0]), .mux_output(mux_output) );
+
+endmodule

src/components/tests/test_mux.sv

@@ -4,41 +4,74 @@ module test_mux ();
 
     parameter N = 32;
 
-    logic [N-1:0] mux_input_1;
-    logic [N-1:0] mux_input_2;
-    logic mux_select;
+    logic [N-1:0] mux_input_1, mux_input_2, mux_input_3, mux_input_4;
+
+    logic mux_select_1bit;
+    logic [1:0] mux_select_2bit;
 
-    wire [N-1:0] mux_output_1;
+    wire [N-1:0] mux_output_1, mux_output_2;
 
-    mux_2_1 mux21_a(.input_1(mux_input_1), .input_2(mux_input_2), .select(mux_select), .mux_output(mux_output_1));
+    mux_2_1 mux21_a(.input_1(mux_input_1), .input_2(mux_input_2), .select(mux_select_1bit), .mux_output(mux_output_1));
+    mux_4_1 mux41_a(.input_1(mux_input_1), .input_2(mux_input_2), .input_3(mux_input_3), .input_4(mux_input_4), .select(mux_select_2bit), .mux_output(mux_output_2));
 
 
-
-
     initial begin
-
-        for(integer i1=0; i1 < 31; i1++) begin
-            for(integer i2 = 0; i2 < 31; i2++) begin
+
+        for(integer test_cases=0; test_cases<1000; test_cases++) begin
                 /* Test Mux 2-to-1 */
-                mux_input_1 = (1 << i1);
-                mux_input_2 = (1 << i2);
-                mux_select = 0;
+                mux_input_1 = $urandom();
+                mux_input_2 = $urandom();
+                mux_input_3 = $urandom();
+                mux_input_4 = $urandom();
+
+                mux_select_1bit = 0;
+                #100;
 
+                $display("mux_input_1 %d mux_input_2 %d mux_select %d mux_output_1 %d", mux_input_1, mux_input_2, mux_select_1bit, mux_output_1);
+                assert(mux_output_1 == mux_input_1);
+
+
+                mux_select_1bit = 1;
                 #100;
-                $display("mux_input_1 %d mux_input_2 %d mux_select %d mux_output_1 %d", mux_input_1, mux_input_2, mux_select, mux_output_1);
+
+                $display("mux_input_1 %d mux_input_2 %d mux_select %d mux_output_1 %d", mux_input_1, mux_input_2, mux_select_1bit, mux_output_1);
                 assert(mux_output_1 == mux_input_2);
 
+                /* Test Mux 4-to-1 */
+                mux_select_2bit = 0; 
+                #100;
+
+
+                $display("mux_input_1 %d mux_input_2 %d mux_input_3 %d mux_input_4 %d mux_select %d mux_output_1 %d", mux_input_1, mux_input_2, mux_input_3, mux_input_4, mux_select_2bit, mux_output_2);
+                assert(mux_input_1 == mux_output_2);
 
-                mux_select = 1;
+                mux_select_2bit = 1; 
                 #100;
 
-                $display("mux_input_1 %d mux_input_2 %d mux_select %d mux_output_1 %d", mux_input_1, mux_input_2, mux_select, mux_output_1);
-                assert(mux_output_1 == mux_input_1);
+                $display("mux_input_1 %d mux_input_2 %d mux_input_3 %d mux_input_4 %d mux_select %d mux_output_1 %d", mux_input_1, mux_input_2, mux_input_3, mux_input_4, mux_select_2bit, mux_output_2);
+                assert(mux_input_2 == mux_output_2);
 
-            end
-        end
+                mux_select_2bit = 2; 
+                #100;
+
+                $display("mux_input_1 %d mux_input_2 %d mux_input_3 %d mux_input_4 %d mux_select %d mux_output_1 %d", mux_input_1, mux_input_2, mux_input_3, mux_input_4, mux_select_2bit, mux_output_2);
+                assert(mux_input_3 == mux_output_2);
+
+
+                mux_select_2bit = 3; 
+                #100;
 
+                $display("mux_input_1 %d mux_input_2 %d mux_input_3 %d mux_input_4 %d mux_select %d mux_output_1 %d", mux_input_1, mux_input_2, mux_input_3, mux_input_4, mux_select_2bit, mux_output_2);
+                assert(mux_input_4 == mux_output_2);
 
+
+
+
+
+                $display("random test iteration %d", test_cases);
+        end
+
+
         $finish;
     end
 endmodule