refactor(pci): migrate PciCommand to pci_types::CommandRegister

Signed-off-by: Martin Kröning <martin.kroening@eonerc.rwth-aachen.de>

src/arch/aarch64/kernel/pci.rs

@@ -5,13 +5,14 @@ use arm_gic::gicv3::{IntId, Trigger};
 use bit_field::BitField;
 use hermit_dtb::Dtb;
 use pci_types::{
-	Bar, ConfigRegionAccess, InterruptLine, InterruptPin, PciAddress, PciHeader, MAX_BARS,
+	Bar, CommandRegister, ConfigRegionAccess, InterruptLine, InterruptPin, PciAddress, PciHeader,
+	MAX_BARS,
 };
 
 use crate::arch::aarch64::kernel::interrupts::GIC;
 use crate::arch::aarch64::mm::paging::{self, BasePageSize, PageSize, PageTableEntryFlags};
 use crate::arch::aarch64::mm::{virtualmem, PhysAddr, VirtAddr};
-use crate::drivers::pci::{PciCommand, PciDevice, PCI_DEVICES};
+use crate::drivers::pci::{PciDevice, PCI_DEVICES};
 use crate::kernel::boot_info;
 
 const PCI_MAX_DEVICE_NUMBER: u8 = 32;
@@ -287,7 +288,7 @@ pub fn init() {
 							let dev = PciDevice::new(pci_address, pci_config);
 
 							// Initializes BARs
-							let mut cmd = PciCommand::default();
+							let mut cmd = CommandRegister::empty();
 							for i in 0..MAX_BARS {
 								if let Some(bar) = dev.get_bar(i.try_into().unwrap()) {
 									match bar {
@@ -299,14 +300,14 @@ pub fn init() {
 												},
 											);
 											io_start += 0x20;
-											cmd |= PciCommand::PCI_COMMAND_IO
-												| PciCommand::PCI_COMMAND_MASTER;
+											cmd |= CommandRegister::IO_ENABLE
+												| CommandRegister::BUS_MASTER_ENABLE;
 										}
 										// Currently, we ignore 32 bit memory bars
 										/*Bar::Memory32 { address, size, prefetchable } => {
 											dev.set_bar(i.try_into().unwrap(), Bar::Memory32 { address: mem32_start.try_into().unwrap(), size,  prefetchable });
 											mem32_start += u64::from(size);
-											cmd |= PciCommand::PCI_COMMAND_MEMORY|PciCommand::PCI_COMMAND_MASTER;
+											cmd |= CommandRegister::MEMORY_ENABLE | CommandRegister::BUS_MASTER_ENABLE;
 										}*/
 										Bar::Memory64 {
 											address: _,
@@ -322,8 +323,8 @@ pub fn init() {
 												},
 											);
 											mem64_start += size;
-											cmd |= PciCommand::PCI_COMMAND_MEMORY
-												| PciCommand::PCI_COMMAND_MASTER;
+											cmd |= CommandRegister::MEMORY_ENABLE
+												| CommandRegister::BUS_MASTER_ENABLE;
 										}
 										_ => {}
 									}

src/drivers/net/virtio_pci.rs

@@ -5,11 +5,12 @@
 use alloc::vec::Vec;
 use core::str::FromStr;
 
+use pci_types::CommandRegister;
 use smoltcp::phy::ChecksumCapabilities;
 
 use crate::arch::pci::PciConfigRegion;
 use crate::drivers::net::virtio_net::{CtrlQueue, NetDevCfg, RxQueues, TxQueues, VirtioNetDriver};
-use crate::drivers::pci::{PciCommand, PciDevice};
+use crate::drivers::pci::PciDevice;
 use crate::drivers::virtio::error::{self, VirtioError};
 use crate::drivers::virtio::transport::pci;
 use crate::drivers::virtio::transport::pci::{PciCap, UniCapsColl};
@@ -163,7 +164,7 @@ impl VirtioNetDriver {
 		device: &PciDevice<PciConfigRegion>,
 	) -> Result<VirtioNetDriver, VirtioError> {
 		// enable bus master mode
-		device.set_command(PciCommand::PCI_COMMAND_MASTER);
+		device.set_command(CommandRegister::BUS_MASTER_ENABLE);
 
 		let mut drv = match pci::map_caps(device) {
 			Ok(caps) => match VirtioNetDriver::new(caps, device) {

src/drivers/pci.rs

@@ -3,14 +3,13 @@
 use alloc::vec::Vec;
 use core::fmt;
 
-use bitflags::bitflags;
 use hermit_sync::without_interrupts;
 #[cfg(any(feature = "tcp", feature = "udp", feature = "fuse"))]
 use hermit_sync::InterruptTicketMutex;
 use pci_types::capability::CapabilityIterator;
 use pci_types::{
-	Bar, ConfigRegionAccess, DeviceId, EndpointHeader, InterruptLine, InterruptPin, PciAddress,
-	PciHeader, StatusRegister, VendorId, MAX_BARS,
+	Bar, CommandRegister, ConfigRegionAccess, DeviceId, EndpointHeader, InterruptLine,
+	InterruptPin, PciAddress, PciHeader, StatusRegister, VendorId, MAX_BARS,
 };
 
 use crate::arch::mm::{PhysAddr, VirtAddr};
@@ -45,34 +44,6 @@ pub(crate) mod constants {
 	pub(crate) const PCI_MASK_IS_DEV_BUS_MASTER: u32 = 0x0000_0004u32;
 }
 
-bitflags! {
-	#[derive(Default, Clone, Copy, Debug, PartialEq, Eq, Hash)]
-	pub struct PciCommand: u32 {
-		/// Enable response in I/O space
-		const PCI_COMMAND_IO = 0x1;
-		/// Enable response in Memory space
-		const PCI_COMMAND_MEMORY = 0x2;
-		/// Enable bus mastering
-		const PCI_COMMAND_MASTER = 0x4;
-		/// Enable response to special cycles
-		const PCI_COMMAND_SPECIAL = 0x8;
-		// Use memory write and invalidate
-		const PCI_COMMAND_INVALIDATE = 0x10;
-		/// Enable palette snooping
-		const PCI_COMMAND_VGA_PALETTE = 0x20;
-		/// Enable parity checking
-		const PCI_COMMAND_PARITY = 0x40;
-		/// Enable address/data stepping
-		const PCI_COMMAND_WAIT = 0x80;
-		/// Enable SERR
-		const PCI_COMMAND_SERR = 0x100;
-		///  Device is allowed to generate fast back-to-back transactions;
-		const PCI_COMMAND_FAST_BACK = 0x200;
-		/// INTx# signal is disabled
-		const PCI_COMMAND_INTX_DISABLE = 0x400;
-	}
-}
-
 /// PCI registers offset inside header,
 /// if PCI header is of type 00h (general device).
 #[allow(dead_code, non_camel_case_types)]
@@ -160,12 +131,12 @@ impl<T: ConfigRegionAccess> PciDevice<T> {
 	}
 
 	/// Set flag to the command register
-	pub fn set_command(&self, cmd: PciCommand) {
+	pub fn set_command(&self, cmd: CommandRegister) {
 		unsafe {
 			let mut command = self
 				.access
 				.read(self.address, DeviceHeader::PCI_COMMAND_REGISTER.into());
-			command |= cmd.bits();
+			command |= cmd.bits() as u32;
 			self.access.write(
 				self.address,
 				DeviceHeader::PCI_COMMAND_REGISTER.into(),
@@ -175,11 +146,11 @@ impl<T: ConfigRegionAccess> PciDevice<T> {
 	}
 
 	/// Get value of the command register
-	pub fn get_command(&self) -> PciCommand {
+	pub fn get_command(&self) -> CommandRegister {
 		unsafe {
-			PciCommand::from_bits(
+			CommandRegister::from_bits(
 				self.access
-					.read(self.address, DeviceHeader::PCI_COMMAND_REGISTER.into()),
+					.read(self.address, DeviceHeader::PCI_COMMAND_REGISTER.into()) as u16,
 			)
 			.unwrap()
 		}