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1. e200_opensource e200_opensource Public

   Forked from SI-RISCV/e200_opensource

   Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

   Verilog

2. e203_hbirdv2 e203_hbirdv2 Public

   Forked from riscv-mcu/e203_hbirdv2

   The Ultra-Low Power RISC-V Core

   Verilog

3. project_skeleton_sp21 project_skeleton_sp21 Public

   Forked from EECS150/project_skeleton_sp21

   Verilog

4. cdc cdc Public

   Forked from dpretet/cdc

   Repository gathering basic modules for CDC purpose

   SystemVerilog

5. async_fifo async_fifo Public

   Forked from dpretet/async_fifo

   A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

   Verilog

6. ccd_register ccd_register Public

   Forked from mcavoya/ccd_register

   Verilog HDL Cross Clock Domain Register

   Verilog