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                                      Simple Computer In Verilog

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View Rendered README on Github https://github.com/ibraheemalayan/Simple_Computer_Verilog_Part_2

Simple Computer In Verilog 💻

project 1 phase II in the computer organization course (ENCS2380) at Birzeit University

Partners

👷 Ibraheem Alyan  1201180
👷 Hammam Khaled   1191081

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Project Paper

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Modules

• CPU.v CPU module that can execute the 12 instructions

• MEMORY.v a 384 byte memory (128 cells each is 3 bytes)

• CLK_GEN.v a sample clock generator that inverts the clock signal each 5 ns (full cycle is 10 ns)

• Test_Bench.v the test bench that connects the modules and is the top level file in the simulation

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Running The Simulation

install Icarus Verilog and add its binaries to your shell path then run the following

git clone https://github.com/ibraheemalayan/Simple_Computer_Verilog_Part_2.git
cd Simple_Computer_Verilog_Part_2/modules
iverilog -o compiled_testbench.vvp Test_Bench.v
vvp compiled_testbench.vvp

Then you can read the output of the display statments
OR
open the waves.vcd using a wave viewer (eg: GTKwave)

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Simulations on GTKwave

Visit the link of each simulation to view the Discussion, simulation text output, memory table view, memory loading code, and the high quality images links

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Simulation 1

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Simulation 2

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Simulation 3

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Simulation 4