Skip to content

Commit

Permalink
presets: correction to instr cache preset
Browse files Browse the repository at this point in the history 
Fix mistake introduced in commit
ef1cc48, in which the definition for
PAPI_L2_ICM can realize negative values.

These changes have been tested on the AMD Zen4 architecture using the
Counter Analysis Toolkit.
  • Loading branch information
@dbarry9 @gcongiu
dbarry9 authored and gcongiu committed Dec 15, 2023
1 parent cceb9ef commit ecd10c6
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion src/papi_events.csv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -542,7 +542,7 @@ PRESET,PAPI_L2_DCH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_
PRESET,PAPI_TLB_IM,DERIVED_ADD,L1_ITLB_MISS_L2_ITLB_HIT,L1_ITLB_MISS_L2_ITLB_MISS:COALESCED4K:IF1G:IF2M:IF4K
PRESET,PAPI_L2_ICR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ:L2_HW_PF
PRESET,PAPI_L2_ICM,DERIVED_SUB,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ:L2_HW_PF,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_HIT_X:IC_FILL_HIT_S
PRESET,PAPI_L2_ICM,DERIVED_SUB,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_MISS
PRESET,PAPI_L2_ICH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_HIT_X:IC_FILL_HIT_S


Expand Down

0 comments on commit ecd10c6

Please sign in to comment.