Skip to content

Commit

Permalink
Derive SAI blocks for 1176 from SAI1
Browse files Browse the repository at this point in the history 
All SAI instances can derive their register blocks from SAI1. While not
every instance has multiple tx/rx lines and fifos the register layout
can be reused for all SAI instances. The mcux sdk actually does this
by casting the instance address to I2S_Type* which is a common struct
with a common register layout.
  • Loading branch information
@SpinFast
SpinFast committed Dec 19, 2023
1 parent 584f3a9 commit df44f52
Show file tree
Hide file tree
Showing 5 changed files with 137 additions and 74 deletions.
3 changes: 3 additions & 0 deletions devices/imxrt1176_cm4.yaml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -108,6 +108,9 @@ _derive:
GPIO11: GPIO2
GPIO12: GPIO2
GPIO13: GPIO2
SAI2: SAI1
SAI3: SAI1
SAI4: SAI1

# All of the directives below this comment are removing or simplifying
# duplicated enumeratedValue fields in select register fields. These prevent
Expand Down
6 changes: 6 additions & 0 deletions devices/imxrt1176_cm7.yaml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,12 @@ _add:
size: 0x14
usage: registers

# SAI[2-4] should reuse the register block from SAI1
_derive:
SAI2: SAI1
SAI3: SAI1
SAI4: SAI1

# All of the directives below this comment are removing or simplifying
# duplicated enumeratedValue fields in select register fields. These prevent
# compilation due to duplicate symbols.
Expand Down
104 changes: 90 additions & 14 deletions src/blocks/imxrt1176_cm4/sai.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,11 +18,11 @@ pub struct RegisterBlock {
#[doc = "Transmit Configuration 5"]
pub TCR5: crate::RWRegister<u32>,
#[doc = "Transmit Data"]
pub TDR0: crate::RWRegister<u32>,
_reserved0: [u8; 0x1c],
pub TDR: [crate::RWRegister<u32>; 4usize],
_reserved0: [u8; 0x10],
#[doc = "Transmit FIFO"]
pub TFR0: crate::RORegister<u32>,
_reserved1: [u8; 0x1c],
pub TFR: [crate::RORegister<u32>; 4usize],
_reserved1: [u8; 0x10],
#[doc = "Transmit Mask"]
pub TMR: crate::RWRegister<u32>,
_reserved2: [u8; 0x24],
Expand All @@ -39,11 +39,11 @@ pub struct RegisterBlock {
#[doc = "Receive Configuration 5"]
pub RCR5: crate::RWRegister<u32>,
#[doc = "Receive Data"]
pub RDR0: crate::RORegister<u32>,
_reserved3: [u8; 0x1c],
pub RDR: [crate::RORegister<u32>; 4usize],
_reserved3: [u8; 0x10],
#[doc = "Receive FIFO"]
pub RFR0: crate::RORegister<u32>,
_reserved4: [u8; 0x1c],
pub RFR: [crate::RORegister<u32>; 4usize],
_reserved4: [u8; 0x10],
#[doc = "Receive Mask"]
pub RMR: crate::RWRegister<u32>,
}
Expand Down Expand Up @@ -471,7 +471,15 @@ pub mod TCR3 {
#[doc = "Transmit Channel Enable"]
pub mod TCE {
pub const offset: u32 = 16;
pub const mask: u32 = 0x01 << offset;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {}
}
#[doc = "Channel FIFO Reset"]
pub mod CFR {
pub const offset: u32 = 24;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {}
Expand Down Expand Up @@ -588,6 +596,23 @@ pub mod TCR4 {
pub const FPACK_3: u32 = 0x03;
}
}
#[doc = "FIFO Combine Mode"]
pub mod FCOMB {
pub const offset: u32 = 26;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "FIFO combine mode disabled."]
pub const FCOMB_0: u32 = 0;
#[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers)."]
pub const FCOMB_1: u32 = 0x01;
#[doc = "FIFO combine mode enabled on FIFO writes (by software)."]
pub const FCOMB_2: u32 = 0x02;
#[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software)."]
pub const FCOMB_3: u32 = 0x03;
}
}
#[doc = "FIFO Continue on Error"]
pub mod FCONT {
pub const offset: u32 = 28;
Expand Down Expand Up @@ -630,7 +655,7 @@ pub mod TCR5 {
}
}
#[doc = "Transmit Data"]
pub mod TDR0 {
pub mod TDR {
#[doc = "Transmit Data Register"]
pub mod TDR {
pub const offset: u32 = 0;
Expand All @@ -641,7 +666,7 @@ pub mod TDR0 {
}
}
#[doc = "Transmit FIFO"]
pub mod TFR0 {
pub mod TFR {
#[doc = "Read FIFO Pointer"]
pub mod RFP {
pub const offset: u32 = 0;
Expand All @@ -658,6 +683,19 @@ pub mod TFR0 {
pub mod W {}
pub mod RW {}
}
#[doc = "Write Channel Pointer"]
pub mod WCP {
pub const offset: u32 = 31;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "No effect."]
pub const WCP_0: u32 = 0;
#[doc = "FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write."]
pub const WCP_1: u32 = 0x01;
}
}
}
#[doc = "Transmit Mask"]
pub mod TMR {
Expand Down Expand Up @@ -1042,7 +1080,15 @@ pub mod RCR3 {
#[doc = "Receive Channel Enable"]
pub mod RCE {
pub const offset: u32 = 16;
pub const mask: u32 = 0x01 << offset;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {}
}
#[doc = "Channel FIFO Reset"]
pub mod CFR {
pub const offset: u32 = 24;
pub const mask: u32 = 0x0f << offset;
pub mod R {}
pub mod W {}
pub mod RW {}
Expand Down Expand Up @@ -1146,6 +1192,23 @@ pub mod RCR4 {
pub const FPACK_3: u32 = 0x03;
}
}
#[doc = "FIFO Combine Mode"]
pub mod FCOMB {
pub const offset: u32 = 26;
pub const mask: u32 = 0x03 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "FIFO combine mode disabled."]
pub const FCOMB_0: u32 = 0;
#[doc = "FIFO combine mode enabled on FIFO writes (from receive shift registers)."]
pub const FCOMB_1: u32 = 0x01;
#[doc = "FIFO combine mode enabled on FIFO reads (by software)."]
pub const FCOMB_2: u32 = 0x02;
#[doc = "FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software)."]
pub const FCOMB_3: u32 = 0x03;
}
}
#[doc = "FIFO Continue on Error"]
pub mod FCONT {
pub const offset: u32 = 28;
Expand Down Expand Up @@ -1188,7 +1251,7 @@ pub mod RCR5 {
}
}
#[doc = "Receive Data"]
pub mod RDR0 {
pub mod RDR {
#[doc = "Receive Data Register"]
pub mod RDR {
pub const offset: u32 = 0;
Expand All @@ -1199,7 +1262,7 @@ pub mod RDR0 {
}
}
#[doc = "Receive FIFO"]
pub mod RFR0 {
pub mod RFR {
#[doc = "Read FIFO Pointer"]
pub mod RFP {
pub const offset: u32 = 0;
Expand All @@ -1208,6 +1271,19 @@ pub mod RFR0 {
pub mod W {}
pub mod RW {}
}
#[doc = "Receive Channel Pointer"]
pub mod RCP {
pub const offset: u32 = 15;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "No effect."]
pub const RCP_0: u32 = 0;
#[doc = "FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read."]
pub const RCP_1: u32 = 0x01;
}
}
#[doc = "Write FIFO Pointer"]
pub mod WFP {
pub const offset: u32 = 16;
Expand Down
49 changes: 19 additions & 30 deletions src/imxrt1176_cm4.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4562,6 +4562,8 @@ pub mod rtwdog {
}
#[path = "."]
pub mod sai {
#[doc = "SAI"]
pub const SAI1: *const RegisterBlock = 0x4040_4000 as *const RegisterBlock;
#[doc = "SAI"]
pub const SAI2: *const RegisterBlock = 0x4040_8000 as *const RegisterBlock;
#[doc = "SAI"]
Expand All @@ -4572,6 +4574,20 @@ pub mod sai {
mod blocks;
pub use blocks::*;
pub type Instance<const N: u8> = crate::Instance<RegisterBlock, N>;
pub type SAI1 = Instance<1>;
impl crate::private::Sealed for SAI1 {}
impl crate::Valid for SAI1 {}
impl SAI1 {
#[doc = r" Acquire a vaild, but possibly aliased, instance."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" See [the struct-level safety documentation](crate::Instance)."]
#[inline]
pub const unsafe fn instance() -> Self {
Instance::new(SAI1)
}
}
pub type SAI2 = Instance<2>;
impl crate::private::Sealed for SAI2 {}
impl crate::Valid for SAI2 {}
Expand Down Expand Up @@ -4616,40 +4632,13 @@ pub mod sai {
}
#[doc = r" Returns the instance number `N` for a peripheral instance."]
pub fn number(rb: *const RegisterBlock) -> Option<u8> {
[(SAI2, 2), (SAI3, 3), (SAI4, 4)]
[(SAI1, 1), (SAI2, 2), (SAI3, 3), (SAI4, 4)]
.into_iter()
.find(|(ptr, _)| core::ptr::eq(rb, *ptr))
.map(|(_, inst)| inst)
}
}
#[path = "."]
pub mod sai1 {
#[doc = "SAI"]
pub const SAI1: *const RegisterBlock = 0x4040_4000 as *const RegisterBlock;
#[path = "blocks/imxrt1176_cm4/sai1.rs"]
mod blocks;
pub use blocks::*;
pub type Instance<const N: u8> = crate::Instance<RegisterBlock, N>;
pub type SAI1 = Instance<{ crate::SOLE_INSTANCE }>;
impl crate::private::Sealed for SAI1 {}
impl crate::Valid for SAI1 {}
impl SAI1 {
#[doc = r" Acquire a vaild, but possibly aliased, instance."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" See [the struct-level safety documentation](crate::Instance)."]
#[inline]
pub const unsafe fn instance() -> Self {
Instance::new(SAI1)
}
}
#[doc = r" Returns the instance number `N` for a peripheral instance."]
pub fn number(rb: *const RegisterBlock) -> Option<u8> {
core::ptr::eq(rb, SAI1).then_some(0)
}
}
#[path = "."]
pub mod sema4 {
#[doc = "IPS_Semaphores"]
pub const SEMA4: *const RegisterBlock = 0x40cc_8000 as *const RegisterBlock;
Expand Down Expand Up @@ -5640,10 +5629,10 @@ pub struct Instances {
pub RDC_SEMAPHORE2: rdc_semaphore::RDC_SEMAPHORE2,
pub RTWDOG3: rtwdog::RTWDOG3,
pub RTWDOG4: rtwdog::RTWDOG4,
pub SAI1: sai::SAI1,
pub SAI2: sai::SAI2,
pub SAI3: sai::SAI3,
pub SAI4: sai::SAI4,
pub SAI1: sai1::SAI1,
pub SEMA4: sema4::SEMA4,
pub SEMC: semc::SEMC,
pub SNVS: snvs::SNVS,
Expand Down Expand Up @@ -5845,10 +5834,10 @@ impl Instances {
RDC_SEMAPHORE2: rdc_semaphore::RDC_SEMAPHORE2::instance(),
RTWDOG3: rtwdog::RTWDOG3::instance(),
RTWDOG4: rtwdog::RTWDOG4::instance(),
SAI1: sai::SAI1::instance(),
SAI2: sai::SAI2::instance(),
SAI3: sai::SAI3::instance(),
SAI4: sai::SAI4::instance(),
SAI1: sai1::SAI1::instance(),
SEMA4: sema4::SEMA4::instance(),
SEMC: semc::SEMC::instance(),
SNVS: snvs::SNVS::instance(),
Expand Down
Loading

0 comments on commit df44f52

Please sign in to comment.