0.6.1

Remove the following peripheral instances from the 1176 API. The base address
for these instances is incorrectly NULL.

• OSC_RC_400M
• PHY_LDO
• TMPSNS
• VMBANDGAP

The register blocks remain part of the API. Users who rely on these instances
may still use offset_of! to compute addresses for indirect accesses.

0.5.4

Remove the following peripheral instances from the 1176 API. The base address
for these instances is incorrectly NULL.

• OSC_RC_400M
• PHY_LDO
• TMPSNS
• VMBANDGAP

The register blocks remain part of the API. Users who rely on these instances
may still use offset_of! to compute addresses for indirect accesses.

Also see the 0.6.1 release.

0.6.0

BREAKING Remove the NVIC and SCB peripherals from the 1176. If you need an
API for Cortex-M registers, check out the cortex-m crate.

BREAKING The 1176 GPU2D interrupt is marked as reserved, and it's not
available in the Interrupt enum.

BREAKING In the 1176 API, there is only one SAI module. All SAI instances,
including those that only have a single channel, now appear to support multiple
channels. The user is responsible for making sure their SAI instance can
truly support multiple channels.

BREAKING The flexio1 module is now called flexio for the 1010,
1015, and 1020 families.

BREAKING Rename LPI2C.SIER field "AM1F" to "AM1IE".

BREAKING Rename SRC.SRSR field "LOCKUP" to "LOCKUP_SYSRESETREQ" for 1011,
1015, and 1051 MCUs.

BREAKING Rename CCM.CS1CDR field "FLEXIO1" to "FLEXIO2" for the 1050 and
1060 families.

BREAKING Expose the "TRNG_ACC" field in TRNG.MCTL on the 1015, 1021 MCUs.

BREAKING Rename IOMUXC_GPR.GPR26 field "GPIO_SEL" to "GPIO_MUX1_GPIO_SEL,"
and correct the documentation.

BREAKING Correct the name, documentation of the SNVS.LPCR field "LVD_EN" on
the 1176.

BREAKING Correct the symbols for most IOMUXC *SELECT_INPUT* enum variants.
As a result of this change, symbols for IOMUXC SW_MUX_CTL* and *SW_PAD_CTL*
enum variants may have also changed.

BREAKING Remove deprecated items from the 0.5.1 release.

Drop all register fields that are documented as "reserved" (first word of the
description, all lowercase). Dropping these fields changes the combiner's
approach for combining fieldsets, enabling correct documentation for non-
reserved fields.

Fix the documentation associated with IOMUXC field values.

0.5.3

Exclude interrupt vector table from host build. See #44 for more details.

0.5.2

Add missing FlexSPI, ENC register fields. See #43.

Release v0.5.1 of imxrt-ral

Deprecated The following items will be renamed in the next breaking release:

Deprecated item	New item	Notes
flexio1	flexio	1010, 1015, and 1020 families.
AM1F	AM1IE	LPI2C.SIER field.
LOCKUP	LOCKUP_SYSRESETREQ	SRC.SRSR field.
FLEXIO1_*	FLEXIO2_*	CCM.CS1CDR fields.
GPIO_SEL	GPIO_MUX1_GPIO_SEL	1060 IOMUXC_GPR.GPR26 field.
PWR_GLITCH_EN	LVD_EN	1170 SNVS.LPCR field.

Fix the TRNG peripheral block for the 1015, 1021 families.

Fix FlexIO register fields that describe pin counts, ensuring that they can
represent the 32 pins available for FlexIO2 and FlexIO3. Note that this
increases the field width for FlexIO1, even though this instance only supports
16 pins. FlexIO1 users should take care to only access the lower four bits of
such fields.

Fix the FlexIO timer and shifter counts from four to eight, permitting access
to all available components.