Merge OpenAI Triton commit 755d416
#3058
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Pipelining loops containing `gpu.barrier` may not always be possible because pipeliner reorders the operations in the loop. It is would be possible to analyze if schedule allows for pipelining that would preserve the order between ops issued before the barrier and ones issued after the barrier, however for now we will simply skip such cases.
…#5476) LinearEncodingAttr's interpretation of `elemsPerThread` appears to be different from that of the TypeConverter. For `register=[[0,0],[0,0],[0,0],[0,0]]` for example, LinearEncodingAttr thinks there is 1 element per thread, but the lowering thinks there are 16 (and some for `tt.reshape`). This fixes that by not skipping broadcasted bases when calling `::getElemsPerThread` for registers.
ReduceOp's lowering does not support linear layouts yet, so propagation of linear layouts across `tt.reduce` ops will cause codegen to crash. The codegen routine is generic enough to support linear layouts, so just enable it and add a few tests.
pbchekin
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Dec 21, 2024
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This PR change the Triton base from 82e7a32 to 755d416 (Dec 20).
Pass rate: 98.79%
Please do not squash and merge this PR.