[SYCL] Add tests for some half builtins #880
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@bader Can I ask you for a copy of the logs for failed CI tests? |
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To run this test on OpenCL back-end, the target must support cl_khr_fp16 extension. Intel OpenCL CPU doesn't support it. |
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Is it possible to specify an extension in XFAIL? Or should I just set XFAIL for OpenCL backend? |
bader
changed the title
… fma, fmin, fmax and fmax (#5724) For functions fma, fmin, fmax and fmax adds bf16 builtins to libclc and optimizes half builtins to use half instructions if supported by the device. This PR also contains some changes (everything in clang folder) that have been merged in upstream llvm since last pulldown and are required for building it. There are parts of (something went wrong when merging these, so only parts were merged at first. The changes in this PR are the remainder): https://reviews.llvm.org/D118977 https://reviews.llvm.org/D117887 https://reviews.llvm.org/D119157 Tests for half changes are in intel/llvm-test-suite#880. Tests for bf16 implementations will be added together with adding support for these to runtime in future PRs.
SYCL/Basic/half_builtins.cpp
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| auto A = a_buf.get_access<access::mode::read>(cgh); \ | ||
| auto D = d_buf.get_access<access::mode::write>(cgh); \ | ||
| cgh.parallel_for(N / SZ, \ | ||
| [=](id<1> index) { D[index] = NAME(A[index]); }); \ |
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I think it would be more efficient to have a kernel testing all functions instead of a kernel per function.
I don't know how to apply the same logic for different vector length (i.e. reduce # of test kernels), but we probably can consider allocating more buffers (e.g. one buffer per vector length).
Co-authored-by: Alexey Bader <alexey.bader@intel.com>
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Is this PR waiting for anything? |
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Waiting on code owner review from intel/llvm-reviewers-runtime. |
| // RUN: %ACC_RUN_PLACEHOLDER %t.out | ||
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| // OpenCL CPU driver does not support cl_khr_fp16 extension | ||
| // UNSUPPORTED: cpu && opencl |
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NIT: would it be better to test for the extension support in the source code itself?
Co-authored-by: Alexey Bader <alexey.bader@intel.com>
Co-authored-by: Alexey Bader <alexey.bader@intel.com>
Added tests for some libclc builtins that work on halfs. We will be making some changes to those, but the tests for them can be merged ahead of time.
Tests some of the changes in intel/llvm#5724