LLVM and SPIRV-LLVM-Translator pulldown (WW36) #11102
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Make local helper functions static to avoid symbol name collision.
Memref descriptors contain an `offset` field that denotes the start of the content of the memref relative to the `alignedPtr`. This offset is not considered when converting a memref descriptor to a np.array in the Python runtime library, essentially treating all memrefs as if they had an offset of zero. This patch introduces the necessary pointer arithmetic to find the actual beginning of the memref contents to the memref->numpy conversion functions. There is an ongoing discussion about whether the `offset` field is needed at all in the memref descriptor. Until that is decided, the Python runtime and CRunnerUtils should still correctly implement the offset handling. Related: https://reviews.llvm.org/D157008 Reviewed By: ftynse Differential Revision: https://reviews.llvm.org/D158494
Prefer to use .empty() instead of checking size().
This is irrelevant for the current tests, but makes sense and later changes easier.
While both SPARCv7/v8 and v9 has a register named %fq, they encode it differently, so we need to differentiate between them. Reviewed By: barannikov88 Differential Revision: https://reviews.llvm.org/D157232
This extends support for ASI-tagged loads, stores, and swaps with the new stored-ASI form ([reg+imm] %asi) introduced in v9. CAS instructions are handled differently by the (dis-)assembler, so it will be handled in a separate patch. Reviewed By: barannikov88 Differential Revision: https://reviews.llvm.org/D157233
This completes the support for the CAS instructions. Besides the base CASA and CASXA forms, on v9 the aliases CAS, CASX, CASL, and CASXL are also available. Reviewed By: barannikov88 Differential Revision: https://reviews.llvm.org/D157234
We can implement these similarly to DerivedToBase casts. We just have to walk the class hierarchy, sum the base offsets and subtract it from the current base offset of the pointer. Differential Revision: https://reviews.llvm.org/D149133
…ng to LLVM There are two motivations for this change: 1. It considerably simplifies adding support for the realloc operation to the new buffer deallocation pass by lowering the realloc such that no deallocation operation is inserted and the deallocation pass itself can insert that dealloc 2. The lowering is expressed on a higher level and thus easier to understand, and the lowerings of the memref operations it is composed of don't have to be duplicated in the MemRefToLLVM lowering (also see discussion in https://reviews.llvm.org/D133424) Reviewed By: springerm Differential Revision: https://reviews.llvm.org/D159430
This adds named ASI tag constants (such as #ASI_P and #ASI_P_L) for memory accesses. This patch adds 64-bit/V9 tag names, given that currently the majority of SPARC software targets that arch. Support for 32-bit/V8 tag names will be added in a future patch. Reviewed By: barannikov88 Differential Revision: https://reviews.llvm.org/D157235
This adds some commonly-used instruction aliases from various sources: - GNU - SPARCv9 manual - JPS1 ASR names Reviewed By: barannikov88 Differential Revision: https://reviews.llvm.org/D157236
Rename CheckBaseDerived to something more general and call it in GetPtrField() as well, so we don't crash later in Pointer::toAPValue(). Differential Revision: https://reviews.llvm.org/D149149
This always succeeds. While I'm here, document why we check the size of p0 against the value of VG. Reviewed By: omjavaid Differential Revision: https://reviews.llvm.org/D157845
Differential Revision: https://reviews.llvm.org/D154189
This allows untangling references to underlying IR for various recipes.
These methods are all const and return a new Pointer instance instead of modifying the given instance.
I've added some missing tests for the following cases: 1. Zero- and sign-extends from unpacked vector types to wide, illegal types. For example, %aext = zext <vscale x 4 x i8> %a to <vscale x 4 x i64> 2. Normal loads combined with 1 3. Masked loads combined with 1 Differential Revision: https://reviews.llvm.org/D159192
In some cases where the same mask is used for multiple extending masked loads it can be more efficient to combine the zero- or sign-extend into the load even if it's not a legal or custom operation. This leads to splitting up the extending load into smaller parts, which also requires splitting the mask. For SVE at least this improves the performance of the SPEC benchmark x264 slightly on neoverse-v1 (~0.3%), and at least one other benchmark improves by around 30%. The uplift for SVE seems due to removing the dependencies (vector unpacks) introduced between the loads and the vector operations, since this should increase the level of parallelism. See tests: CodeGen/AArch64/sve-masked-ldst-sext.ll CodeGen/AArch64/sve-masked-ldst-zext.ll https://reviews.llvm.org/D159191
…-Wcast-qual) Functional-style cast (i.e. a simple-type-specifier or typename-specifier followed by a parenthesize single expression [expr.type.conv]) is equivalent to the C-style cast, so that makes sense they have identical behavior including warnings. This also matches GCC https://godbolt.org/z/b8Ma9Thjb. Reviewed By: rnk, aaron.ballman Differential Revision: https://reviews.llvm.org/D159133
This patch: * Replaces `andymckay/labeler` which does not appear to be maintained by github official solution * Removes the closed issue workflow which was disabled a few years ago and never fixed. * Adds a few rules to add label based on PR title, hopefully that can make triaging simpler. If that turns out to be useful, we can consider adding more rules for backends, etc. We could technically also pattern match the body of the issue but I'm concerned about trying to be _too_ clever. The new system is only triggered on PR open so manual labels should not be removed.
Fixes a test which was broken on the green dragon buildbot, and further failures on the SIE buildbot. This reverts commit 8df9eff.
Specification: KhronosGroup/SPIRV-Registry#216 Original commit: KhronosGroup/SPIRV-LLVM-Translator@387841b
Bulk-convert some of the remaining tests using the migration script, while manually ensuring that kernel argument metadata is left unchanged. Original commit: KhronosGroup/SPIRV-LLVM-Translator@613f536
This changes add SPIR-V translator support for the SPIR-V extension documented here: KhronosGroup/SPIRV-Registry#193. This extension adds one decoration to represent maximum error for FP operations and adds the related Capability. SPIRV Headers support for representing this in SPIR-V: KhronosGroup/SPIRV-Headers#363 #8134 added a new call-site attribute associated with FP builtin intrinsics. This attribute is named 'fpbuiltin-max-error'. Following example shows how this extension is supported in the translator. The input LLVM IR uses new LLVM builtin calls to represent FP operations. An attribute named 'fpbuiltin-max-error' is used to represent the max-error allowed in the FP operation. Example Input LLVM: %t6 = call float @llvm.fpbuiltin.sin.f32(float %f1) #2 attributes #2 = { "fpbuiltin-max-error"="2.5" } This is translated into a SPIR-V instruction (for add/sub/mul/div/rem) and OpenCl extended instruction for other instructions. A decoration to represent the max-error is attached to the SPIR-V instruction. SPIR-V code: 4 Decorate 97 FPMaxErrorDecorationINTEL 1075838976 6 ExtInst 2 97 1 sin 88 No new support is added to support translating this SPIR_V back to LLVM. Existing support is used. The decoration is translated back into named metadata associated with the LLVM instruction. This can be readily consumed by backends. Based on input from @andykaylor, we emit attributes when the FP operation is translated back to a call to a builtin function and emit metadata otherwise. Translated LLVM code for basic math functions (add/sub/mul/div/rem): %t6 = fmul float %f1, %f2, !fpbuiltin-max-error !7 !7 = !{!"2.500000"} Translated LLVM code for other math functions: %t6 = call spir_func float @_Z3sinf(float %f1) #3 attributes #3 = { "fpbuiltin-max-error"="4.000000" } Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam@intel.com> Original commit: KhronosGroup/SPIRV-LLVM-Translator@c6fe12b
Fixes the following LIT regressions:
Clang :: SemaSYCL/device_has_ast.cpp
Clang :: SemaSYCL/uses_aspects_ast.cpp
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elizabethandrews
approved these changes
Sep 7, 2023
smanna12
approved these changes
Sep 8, 2023
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/merge |
bb-sycl
approved these changes
Sep 9, 2023
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Sat 09 Sep 2023 12:10:23 AM UTC --- Start to merge the commit into sycl branch. It will take several minutes. |
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Sat 09 Sep 2023 12:14:28 AM UTC --- Merge the branch in this PR to base automatically. Will close the PR later. |
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LLVM: llvm/llvm-project@73b2c86
SPIRV-LLVM-Translator: KhronosGroup/SPIRV-LLVM-Translator@c6fe12b