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27 changes: 16 additions & 11 deletions clang/lib/Driver/ToolChains/SYCL.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -271,17 +271,22 @@ void SYCL::fpga::BackendCompiler::ConstructJob(Compilation &C,
} else {
// Output directory is based off of the first object name
for (Arg * Cur : Args) {
SmallString<128> AN = Cur->getSpelling();
StringRef Ext(llvm::sys::path::extension(AN));
if (!Ext.empty()) {
types::ID Ty = getToolChain().LookupTypeForExtension(Ext.drop_front());
if (Ty == types::TY_INVALID)
continue;
if (types::isSrcFile(Ty) || Ty == types::TY_Object) {
llvm::sys::path::replace_extension(AN, "prj");
ReportOptArg += Args.MakeArgString(AN);
break;
}
if (Cur->getOption().getKind() != Option::InputClass)
continue;
SmallString<128> ArgName = Cur->getSpelling();
StringRef Ext(llvm::sys::path::extension(ArgName));
if (Ext.empty())
continue;
types::ID Ty = getToolChain().LookupTypeForExtension(Ext.drop_front());
if (Ty == types::TY_INVALID)
continue;
if (types::isSrcFile(Ty) || Ty == types::TY_Object) {
// Project report should be saved into CWD, so strip off any
// directory information if provided with the input file.
ArgName = llvm::sys::path::filename(ArgName);
llvm::sys::path::replace_extension(ArgName, "prj");
ReportOptArg += Args.MakeArgString(ArgName);
break;
}
}
}
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10 changes: 10 additions & 0 deletions clang/test/Driver/sycl-offload-intelfpga.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -171,6 +171,16 @@
// RUN: | FileCheck -DOUTDIR=%t_dir -check-prefix=CHK-FPGA-REPORT-OPT %s
// CHK-FPGA-REPORT-OPT: aoc{{.*}} "-sycl" {{.*}} "-output-report-folder=[[OUTDIR]]{{/|\\\\}}file.prj"

/// -fintelfpga output report file from dir/source
// RUN: mkdir -p %t_dir
// RUN: touch %t_dir/dummy.cpp
// RUN: %clangxx -### -fsycl -fintelfpga %t_dir/dummy.cpp 2>&1 \
// RUN: | FileCheck -DOUTDIR=%t_dir -check-prefix=CHK-FPGA-REPORT-OPT2 %s
// RUN: %clang_cl -### -fsycl -fintelfpga %t_dir/dummy.cpp 2>&1 \
// RUN: | FileCheck -DOUTDIR=%t_dir -check-prefix=CHK-FPGA-REPORT-OPT2 %s
// CHK-FPGA-REPORT-OPT2: aoc{{.*}} "-sycl" {{.*}} "-output-report-folder=dummy.prj"
// CHK-FPGA-REPORT-OPT2-NOT: aoc{{.*}} "-sycl" {{.*}} "-output-report-folder=[[OUTDIR]]{{.*}}"

/// -fintelfpga static lib (aoco)
// RUN: echo "Dummy AOCO image" > %t.aoco
// RUN: echo "void foo() {}" > %t.c
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