[SYCL][CUDA] Workaround for the problem with memory reordering #1334
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Currently there is a bug in LLVM for PTX target. PTX target specific intrinsics like llvm.nvvm.barrier0 are treated like regular LLVM intrinsics in Globals AA. As a result, there are situations when Globals AA produces a result that barrier intrinsic doesn't modify internal globals. This allows llvm transformations like GVN to perform illegal memory reordering. This is a workaround while permanent fix is not implemented in LLVM project. Signed-off-by: Artur Gainullin <artur.gainullin@intel.com>
codeplay-sycl
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Oct 21, 2021
This patch attempts to generalise this workaround: intel#1334
AlexeySachkov
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Aug 2, 2023
…y point interfaces (PR #1334) (#10623) This PR pulls in the following PR from upstream Khronos SPIRV-LLVM-Translator repo: KhronosGroup/SPIRV-LLVM-Translator#1334 ` This is a patch to expand the collection of entry point interfaces. In SPIR-V 1.4 and later OpEntryPoint must list all global variables in the interface. ` In addition, a couple of minor changes have been added to sync with latest code. This patch addresses #9958 Updated the following tests to sync with upstream as well: llvm-spirv/test/extensions/INTEL/SPV_INTEL_inline_assembly/inline_asm_clobbers.cl llvm-spirv/test/extensions/INTEL/SPV_INTEL_inline_assembly/inline_asm_constraints.cl Thanks --------- Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam@intel.com>
mdtoguchi
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Oct 18, 2023
…y point interfaces (PR intel#1334) (intel#10623) This PR pulls in the following PR from upstream Khronos SPIRV-LLVM-Translator repo: KhronosGroup/SPIRV-LLVM-Translator#1334 ` This is a patch to expand the collection of entry point interfaces. In SPIR-V 1.4 and later OpEntryPoint must list all global variables in the interface. ` In addition, a couple of minor changes have been added to sync with latest code. This patch addresses intel#9958 Updated the following tests to sync with upstream as well: llvm-spirv/test/extensions/INTEL/SPV_INTEL_inline_assembly/inline_asm_clobbers.cl llvm-spirv/test/extensions/INTEL/SPV_INTEL_inline_assembly/inline_asm_constraints.cl Thanks --------- Signed-off-by: Arvind Sudarsanam <arvind.sudarsanam@intel.com>
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Currently there is a bug in LLVM for PTX target. PTX target specific
intrinsics like llvm.nvvm.barrier0 are treated like regular LLVM
intrinsics in Globals AA. As a result, there are situations when Globals
AA produces a result that barrier intrinsic doesn't modify internal
globals. This allows llvm transformations like GVN to perform illegal
memory reordering.
This is a workaround while permanent fix is not implemented in LLVM
project.
Signed-off-by: Artur Gainullin artur.gainullin@intel.com