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@fabiomestre fabiomestre commented Jun 3, 2025

Optimizes the enqueue() function of sycl graphs to bypass the scheduler whenever possible and avoid creating events when not needed.

  • Refactors the executable graph enqueue() to have different paths depending on workload:
    • The direct path will be used when there are no host-tasks or accessor requirements in the graph and the execution dependencies are considered safe to bypass the scheduler.
    • The scheduler path will be used when there are requirements in the graph but no host-tasks or, if the execution dependencies require using the scheduler.
    • The multiple partitions path will be used when the graph contains host-tasks which requires scheduling multiple graph partitions. The implementation was also changed to avoid adding unnecessary event dependencies to partition executions and avoiding copying CGData when possible.
  • Extends the changes in [SYCL] Do not store last event for in-order queues #18277 to sycl graphs. This means that no implicit events will be created when using in-order queues and graphs without host-tasks. Also updates the handler to only request events from the graph enqueue() when they are needed.

@fabiomestre fabiomestre force-pushed the fabio/eventless_graph_enqueue branch 2 times, most recently from 4c130dc to ad6ed0e Compare June 3, 2025 16:23
@fabiomestre fabiomestre force-pushed the fabio/eventless_graph_enqueue branch from ad6ed0e to e8ee455 Compare June 3, 2025 16:45
@fabiomestre fabiomestre force-pushed the fabio/eventless_graph_enqueue branch from e8ee455 to 8393ea8 Compare June 3, 2025 16:54
@fabiomestre fabiomestre force-pushed the fabio/eventless_graph_enqueue branch 2 times, most recently from b00774f to 130688f Compare June 5, 2025 13:39
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fabiomestre commented Jun 17, 2025

@intel/llvm-gatekeepers Can this PR be merged? The existing failures seem to be CI issues. This PR was green for those jobs before:

Intel-Arc jobs:

Cuda UR Job:

There were only unrelated changes to the HIP UR adapter made since then.

Edit: Nevermind, recently merged commits broke this PR, needs to be rebased.

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@intel/llvm-gatekeepers This PR is ready to merge. The CI failure on PVC is unrelated (I have seen it in other PR's).

@uditagarwal97
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@intel/llvm-gatekeepers This PR is ready to merge. The CI failure on PVC is unrelated (I have seen it in other PR's).

Failing tests are unrelated and tracked by #18932

@uditagarwal97 uditagarwal97 merged commit b643b8b into intel:sycl Jun 18, 2025
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9 participants