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[SYCL] Expanded Ahead Of Time Compilation support #262
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[SYCL] Expanded Ahead Of Time Compilation support #262
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clang/lib/Driver/ToolChains/SYCL.cpp
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CmdArgs.push_back("-cmd=link"); | ||
CmdArgs.push_back("-device=cpu"); | ||
for (const auto &II : Inputs) { | ||
CmdArgs.push_back(Args.MakeArgString(Twine("-binary=") + II.getFilename())); |
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What are the Inputs
here? LLVM IR Bitcode with spir64 triple?
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What are the
Inputs
here? LLVM IR Bitcode with spir64 triple?
Yes, that is the expected input for ioc. Depending on expectations of the tool, this can either be LLVM-IR or SPIR-V.
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This may work for now, but LLVM IR is not a stable interface and older/newer CPU runtime may not consume LLVM IR generated by SYCL clang.
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Be optimistic... :-)
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Changes refactored to remove CPU support for now. CPU support will be added later. |
Can you include an example of compilation commands for 1-step offline compilation for FPGA and GPU? |
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FPGA: clang++ -fsycl -fsycl-targets=spir64_fpga-unknown-linux-sycldevice I also added these command lines to the commit message. |
In general I would be quite interested at some point in the future in seeing some shiny new documentation on the commands added to the driver and how to use all these new commands, maybe that's a silly request though which I can understand. But I think it does help to elaborate a little on it outside of the table gen files/commit logs. I know there is some coverage of this inside of: https://github.com/intel/llvm/blob/sycl/sycl/doc/SYCL_compiler_and_runtime_design.md but I'm not too sure how up-to-date it is (and perhaps there is some documentation elsewhere I'm unaware of). |
Definitely not a silly request. We are working on adding documentation which covers all of the new options being provided.
From: agozillon <notifications@github.com>
Sent: Tuesday, July 09, 2019 10:52 AM
To: intel/llvm <llvm@noreply.github.com>
Cc: Toguchi, Michael D <michael.d.toguchi@intel.com>; Author <author@noreply.github.com>
Subject: Re: [intel/llvm] [SYCL] Expanded Ahead Of Time Compilation support (#262)
In general I would be quite interested at some point in the future in seeing some shiny new documentation on the commands added to the driver and how to use all these new commands, maybe that's a silly request though which I can understand.
But I think it does help to elaborate a little on it outside of the table gen files/commit logs. I know there is some coverage of this inside of: https://github.com/intel/llvm/blob/sycl/sycl/doc/SYCL_compiler_and_runtime_design.md but I'm not too sure how up-to-date it is (and perhaps there is some documentation elsewhere I'm unaware of).
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Any other comments? Would be great to get this in so I can (more easily) work on the AOT CPU enabling work. :) |
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@mdtoguchi, looks good.
I have a couple of suggestions.
Let me know how do you feel about applying them.
I can work on your suggestions and also modify the option names added to match what was decided for the -Xsycl*. |
Great. I'll wait for updated version then. |
Adds support for AOT compilation in a single pass. Support is triggered by using a sub architecture value in the triple. The following 2 are supported: spir64_fpga, spir64_gen When one of these are used, the respective backend compiler (aoc, ocloc) is invoked to perform the AOT compilation. That device binary is then wrapped and included in the final binary. Additional options can also be added to the SYCL device compilation, the Backend compile or the device link. These are handled by -Xsycl-target-frontend, -Xsycl-target-backend or -Xsycl-target-linker respectively Example command lines: FPGA: clang++ -fsycl -fsycl-targets=spir64_fpga-unknown-linux-sycldevice testfile.cpp -Xsycl-target-backend "-DFOO" GEN: clang++ -fsycl -fsycl-targets=spir64_gen-unknown-linux-sycldevice testfile.cpp -Xsycl-target-backend "-device skl" Signed-off-by: Michael D Toguchi <michael.d.toguchi@intel.com>
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I didn't even realize that was still in there. That was from an early implementation! triples are definitely kept around and can be used for compilation. I'll clean it up with the AOT for CPU work.
From: Alexey Bader <notifications@github.com>
Sent: Thursday, July 11, 2019 1:25 AM
To: intel/llvm <llvm@noreply.github.com>
Cc: Toguchi, Michael D <michael.d.toguchi@intel.com>; Mention <mention@noreply.github.com>
Subject: Re: [intel/llvm] [SYCL] Expanded Ahead Of Time Compilation support (#262)
@bader commented on this pull request.
________________________________
In clang/lib/Driver/Driver.cpp<#262 (comment)>:
@@ -3263,6 +3282,43 @@ class OffloadingActionBuilder final {
}
}
}
+ // Gather information about the SYCL Ahead of Time targets. The targets
+ // are determined on the SubArch values passed along in the triple.
+ // The SubArch information for SYCL offload is not used during the
+ // compilation and is only used to determine additional compilation steps
+ // needed in the driver toolchain.
+ Arg *SYCLTargets =
+ C.getInputArgs().getLastArg(options::OPT_fsycl_targets_EQ);
+ if (SYCLTargets) {
+ llvm::StringMap<const char *> FoundNormalizedTriples;
+ for (const char *Val : SYCLTargets->getValues()) {
Okay. Let's ignore this comment.
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Adds support for AOT compilation in a single pass. Support is triggered by
using a sub architecture value in the triple. The following 3 are supported:
spir64_fpga, spir64_x86_64, spir64_gen
When one of these are used, the respective backend compiler (aoc, ioc or cloc)
is invoked to perform the AOT compilation. That device binary is then wrapped
and included in the final binary.
Additional options can also be added to the SYCL device compilation, the
Backend compile or the device link. These are handled by -Xsycl-compiler,
-Xsycl-target or -Xsycl-linker respectively
Signed-off-by: Michael D Toguchi michael.d.toguchi@intel.com