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[NFC][ESIMD] Remove one of the uses of __SYCL_EXPLICIT_SIMD__ #3242

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merged 1 commit into from
Feb 25, 2021

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DenisBakhvalov
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This patch is a part of the efforts for allowing ESIMD and
regular SYCL kernels to coexist in the same translation unit and
in the same program.

In ESIMD kernels, calls to _spirv functions are lowered into GenX intrinsic.
Because of that, it's OK to have definitions instead of declarations for those functions.
Unused definitions of _spirv functions will be DCE'ed anyway, so no impact on functionality.

This patch is a part of the efforts for allowing ESIMD and
regular SYCL kernels to coexist in the same translation unit and
in the same program.

In ESIMD kernels, calls to __spirv_ functions are lowered into GenX intrinsic.
Because of that, it's OK to have definitions instead of declarations for those functions.
Unused definitions of __spirv_ functions will be DCE'ed anyway, so no impact on functionality.
@DenisBakhvalov DenisBakhvalov requested a review from a team as a code owner February 22, 2021 04:15
@romanovvlad romanovvlad merged commit 6b9b16c into intel:sycl Feb 25, 2021
DenisBakhvalov added a commit to DenisBakhvalov/llvm that referenced this pull request Mar 5, 2021
…__ (intel#3242)"

This patch is a part of the efforts for allowing ESIMD and
regular SYCL kernels to coexist in the same translation unit and
in the same program.

Previously, in ESIMD device code we had calls to SPIRV intrinsics
that didn't have definitions. With the change in spirv_vars.hpp,
SYCL optimization passes convert calls to SPIRV intrinsics into
loads from globals (SPIRV builtins). Thus, there is a need to change
the implementation of LowerESIMD pass to lower such new constructs.

Example:

//  @__spirv_BuiltInGlobalInvocationId = external dso_local local_unnamed_addr addrspace(1) constant <3 x i64>, align 32
//  ...
//  %0 = load <3 x i64>, <3 x i64> addrspace(4)* addrspacecast
//       (<3 x i64> addrspace(1)* @__spirv_BuiltInLocalInvocationId
//       to <3 x i64> addrspace(4)*), align 32
//  %1 = extractelement <3 x i64> %0, i64 0
//
//    =>
//
//  %.esimd = call <3 x i32> @llvm.genx.local.id.v3i32()
//  %local_id.x = extractelement <3 x i32> %.esimd, i32 0
//  %local_id.x.cast.ty = zext i32 %local_id.x to i64

Current tests in sycl/test/esimd/spirv_intrins_trans.cpp check that
there is no regression in how we lower SPRIV intrinsics into GenX
counterparts. But also, I added some more tests.
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3 participants