[SYCL] [L0] Add user APIs to import / release host memory from USM. #9294

rdeodhar · 2023-05-03T18:49:32Z

This change adds a SYCL interface to the Level Zero APIs zexDriverImportExternalPointer and zexDriverReleaseImportedPointer. These functions are used for importing host memory into USM for the duration of data transfer to increase bandwidth.

jchlanda · 2023-05-11T09:18:26Z

CUDA and HIP LGTM.

However, I wonder if this has to be a oneapi-wide extension, would it not be better suited as sycl_ext_intel_...? It is a noop for all but L0 backends and seems unlikely that it will ever change.
Alternatively, would it be possible, instead of creating new PI entries, have logic in prepare_for_device_copy and friends that dispatches to correct L0 free functions?

rdeodhar · 2023-05-12T20:27:35Z

Although the implementation has been fleshed out for L0, the intent is to allow other platforms to do what is necessary to accelerate host<->device transfers within the range of the prepare / release.

sycl/doc/extensions/experimental/sycl_ext_oneapi_usm_prepare_release_device_copy.asciidoc

sycl/plugins/level_zero/pi_level_zero.cpp

jandres742 · 2023-05-19T22:40:22Z

sycl/plugins/cuda/pi_cuda.cpp

  return result;
 }

+pi_result piextUSMImport(void *ptr, size_t size, pi_context context) {


we have something similar in CU, cudaHostRegister, cudaHostUnregister . should we expand the definition of the extension to cover the functionality offered by all backends?

Moreover, the L0 APIs are driver-experimental extensions, and when merged to the spec, they would likely be much different. i dont think that we should define a SYCL extension until the L0 interfaces are at least defined in the L0 spec.

It is not quite equivalent to the cuda HostRegister APIs. Those make the address range accessible from host and device and in addition pin the host memory to physical memory. We should add "pinning" as a separate extension when it is supported by L0.

thanks @rdeodhar . Now that we are moving to the UR, all PI interfaces should be designed taking into account all interfaces. Or maybe, something like UR extensions would help here. I will bring up this in the UR WGs.

Moreover, the L0 APIs are driver-experimental extensions, and when merged to the spec, they would likely be much different. i dont think that we should define a SYCL extension until the L0 interfaces are at least defined in the L0 spec.

Note that this is also an experimental SYCL extension. We can replace it with a more general API later if the L0 API changes.

@gmlueck : Even if this is an experimental extension, we need UR interfaces for it.

I agree. I was only responding to your comment that I quoted, where you seemed to be implying that we should not have SYCL APIs that expose experimental L0 features.

@rdeodhar Documentation on how to support experimental features is still being written by @kbenzie, but the draft PR is here: oneapi-src/unified-runtime#546

As this is experimental the UR experimental feature can look identical to the PI feature if that is the quickest way to keep this PR moving.

You can also ask us (@alycm, @jandres742, @kbenzie) any questions and we'll help you out.

dm-vodopyanov · 2023-07-19T20:31:17Z

Failure in post-commit: build failed on Linux and macOS.
@rdeodhar could you please fix ASAP?

…ntel#9294) This change adds a SYCL interface to the Level Zero APIs zexDriverImportExternalPointer and zexDriverReleaseImportedPointer. These functions are used for importing host memory into USM for the duration of data transfer to increase bandwidth.

rdeodhar added 3 commits May 3, 2023 11:46

[SYCL] [L0] Add user APIs to import / release host memory from USM.

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Minor change.

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Merge branch 'sycl' of https://github.com/intel/llvm into l0import

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rdeodhar marked this pull request as ready for review May 6, 2023 20:20

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rdeodhar requested review from bso-intel and jchlanda May 6, 2023 20:20

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Merge branch 'sycl' of https://github.com/intel/llvm into l0import

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Merge branch 'sycl' of https://github.com/intel/llvm into l0import

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Merge branch 'sycl' of https://github.com/intel/llvm into l0import

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rdeodhar added 2 commits July 18, 2023 10:27

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againull merged commit 65cc0cf into intel:sycl Jul 19, 2023

dm-vodopyanov mentioned this pull request Jul 19, 2023

[SYCL] [L0] Fix for unreferenced parameters. #10476

Merged

TApplencourt mentioned this pull request Apr 10, 2025

prepare_for_device_copy doesn't work like malloc_host #17935

Closed

[SYCL] [L0] Add user APIs to import / release host memory from USM. #9294

[SYCL] [L0] Add user APIs to import / release host memory from USM. #9294

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