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[SYCL][UR][L0] Port PI L0 environment variables to UR L0 #9300

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aelovikov-intel merged 1 commit into from
May 8, 2023
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[SYCL][UR][L0] Port PI L0 environment variables to UR L0 #9300

aelovikov-intel merged 1 commit into from
May 8, 2023

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@jandres742 jandres742 commented May 4, 2023

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[SYCL][UR][L0] Port PI L0 environment variables to UR L0
d1cdeba 
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
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@jandres742 jandres742 marked this pull request as ready for review May 6, 2023 12:52
@jandres742 jandres742 requested a review from a team as a code owner May 6, 2023 12:52
smaslov-intel
smaslov-intel approved these changes May 6, 2023
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We need to start documenting new UR env vars (currently documented here under SYCL):

https://github.com/intel/llvm/blob/sycl/sycl/doc/EnvironmentVariables.md#controlling-dpc-level-zero-plugin
https://github.com/intel/llvm/blob/sycl/sycl/doc/EnvironmentVariables.md#debugging-variables-for-level-zero-plugin

Perhaps this PR is a good time to do so, but I am also OK if this is done in a subsequent PR.

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jandres742 commented May 6, 2023

We need to start documenting new UR env vars (currently documented here under SYCL):

https://github.com/intel/llvm/blob/sycl/sycl/doc/EnvironmentVariables.md#controlling-dpc-level-zero-plugin https://github.com/intel/llvm/blob/sycl/sycl/doc/EnvironmentVariables.md#debugging-variables-for-level-zero-plugin

Perhaps this PR is a good time to do so, but I am also OK if this is done in a subsequent PR.

Thanks @smaslov-intel . Good idea. Please see this PR addressing the documentation #9350

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jandres742 commented May 8, 2023

@intel/llvm-gatekeepers : could we merget this?

@aelovikov-intel aelovikov-intel merged commit 9cf7ee4 into intel:sycl May 8, 2023
jandres742 pushed a commit to jandres742/llvm that referenced this pull request May 16, 2023
Port Port PI L0 environment variables to UR L0
eb936f6 
intel#9300

Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
jandres742 pushed a commit to jandres742/llvm that referenced this pull request May 23, 2023
Port Port PI L0 environment variables to UR L0
6adb8bf 
intel#9300

Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
jandres742 pushed a commit to jandres742/llvm that referenced this pull request May 26, 2023
Port Port PI L0 environment variables to UR L0
5eaf7f3 
intel#9300

Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
veselypeta pushed a commit to veselypeta/llvm that referenced this pull request Sep 21, 2023
[SYCL][UR][L0] Port PI L0 environment variables to UR L0 (intel#9300)
6c1c4a7 
Signed-off-by: Jaime Arteaga <jaime.a.arteaga.molina@intel.com>
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