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Deprecations on Logic in favor of value's isValid and isFloating (#216)
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priya-t12 authored Feb 1, 2023
1 parent e823fa9 commit a5101dd
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Showing 3 changed files with 5 additions and 3 deletions.
2 changes: 2 additions & 0 deletions lib/src/logic.dart
Original file line number Diff line number Diff line change
Expand Up @@ -335,9 +335,11 @@ class Logic {
BigInt get valueBigInt => value.toBigInt();

/// Returns `true` iff the value of this signal is valid (no `x` or `z`).
@Deprecated('Use value.isValid instead.')
bool hasValidValue() => value.isValid;

/// Returns `true` iff *all* bits of the current value are floating (`z`).
@Deprecated('Use value.isFloating instead.')
bool isFloating() => value.isFloating;

/// The [Logic] signal that is driving `this`, if any.
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2 changes: 1 addition & 1 deletion lib/src/modules/gates.dart
Original file line number Diff line number Diff line change
Expand Up @@ -725,7 +725,7 @@ class IndexGate extends Module with InlineSystemVerilog, FullyCombinational {

/// Executes the functional behavior of this gate.
void _execute() {
if (_index.hasValidValue() && _index.value.toInt() < _original.width) {
if (_index.value.isValid && _index.value.toInt() < _original.width) {
final indexVal = _index.value.toInt();
final outputValue = _original.value.getRange(indexVal, indexVal + 1);
selection.put(outputValue);
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4 changes: 2 additions & 2 deletions lib/src/synthesizers/systemverilog.dart
Original file line number Diff line number Diff line change
Expand Up @@ -398,9 +398,9 @@ class _SynthModuleDefinition {
}
assignments.add(_SynthAssignment(synthDriver, synthReceiver));
}
} else if (driver == null && receiver.hasValidValue()) {
} else if (driver == null && receiver.value.isValid) {
assignments.add(_SynthAssignment(receiver.value, synthReceiver));
} else if (driver == null && !receiver.isFloating()) {
} else if (driver == null && !receiver.value.isFloating) {
// this is a signal that is *partially* invalid (e.g. 0b1z1x0)
assignments.add(_SynthAssignment(receiver.value, synthReceiver));
}
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