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Swizzling a 0-bit signal creates invalid SystemVerilog with 0-width signals in it. For example:
assign b = {0'h0,a}; // swizzle
Swizzle a 0-width Const and generate SystemVerilog.
Const
The 0-width signal is omitted from the generated SystemVerilog.
The text was updated successfully, but these errors were encountered:
fix intel#122
587a6e2
Logic
LogicValue
mkorbel1
Successfully merging a pull request may close this issue.
Describe the bug
Swizzling a 0-bit signal creates invalid SystemVerilog with 0-width signals in it. For example:
To Reproduce
Swizzle a 0-width
Const
and generate SystemVerilog.Expected behavior
The 0-width signal is omitted from the generated SystemVerilog.
The text was updated successfully, but these errors were encountered: