Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Swizzling 0-bit signals improperly creates 0-bit generated SystemVerilog #122

Closed
mkorbel1 opened this issue May 5, 2022 · 0 comments · Fixed by #121
Closed

Swizzling 0-bit signals improperly creates 0-bit generated SystemVerilog #122

mkorbel1 opened this issue May 5, 2022 · 0 comments · Fixed by #121
Assignees
@mkorbel1
Labels
bug Something isn't working

Comments

@mkorbel1
Copy link
Contributor

mkorbel1 commented May 5, 2022

Describe the bug

Swizzling a 0-bit signal creates invalid SystemVerilog with 0-width signals in it. For example:

assign b = {0'h0,a};  // swizzle

To Reproduce

Swizzle a 0-width Const and generate SystemVerilog.

Expected behavior

The 0-width signal is omitted from the generated SystemVerilog.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees

@mkorbel1 mkorbel1

Labels
bug Something isn't working
Projects
None yet
Milestone
No milestone
Development

Successfully merging a pull request may close this issue.

Various features and testing for Logic and LogicValue mkorbel1/rohd
1 participant
@mkorbel1