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Generated SystemVerilog from ROHD will be unsized like 0 or 15 instead of with an explicit size like 2'b0 and 16'd15. This can cause anything from a lint failure to a swizzling width mismatch/misalignment.
To Reproduce
Generate SystemVerilog with constant value assignments using Const.
Expected behavior
All constants are sized.
Actual behavior
No constants are sized.
The text was updated successfully, but these errors were encountered:
Describe the bug
Generated SystemVerilog from ROHD will be unsized like
0
or15
instead of with an explicit size like2'b0
and16'd15
. This can cause anything from a lint failure to a swizzling width mismatch/misalignment.To Reproduce
Generate SystemVerilog with constant value assignments using
Const
.Expected behavior
All constants are sized.
Actual behavior
No constants are sized.
The text was updated successfully, but these errors were encountered: