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Constants in generated SystemVerilog are unsized #89

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mkorbel1 opened this issue Mar 24, 2022 · 0 comments · Fixed by #94
Closed

Constants in generated SystemVerilog are unsized #89

mkorbel1 opened this issue Mar 24, 2022 · 0 comments · Fixed by #94
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Describe the bug

Generated SystemVerilog from ROHD will be unsized like 0 or 15 instead of with an explicit size like 2'b0 and 16'd15. This can cause anything from a lint failure to a swizzling width mismatch/misalignment.

To Reproduce

Generate SystemVerilog with constant value assignments using Const.

Expected behavior

All constants are sized.

Actual behavior

No constants are sized.
@mkorbel1 mkorbel1 added the bug Something isn't working label Mar 24, 2022
@mkorbel1 mkorbel1 self-assigned this Mar 24, 2022
@mkorbel1 mkorbel1 mentioned this issue Mar 28, 2022
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Add explicit width to Const generated SystemVerilog mkorbel1/rohd
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