Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

_Wires underneath Logics #199

Merged
merged 9 commits into from
Dec 1, 2022
Merged

_Wires underneath Logics #199

merged 9 commits into from
Dec 1, 2022

Conversation

mkorbel1
Copy link
Contributor

Description & Motivation

Refactored Logic to hold its value on a _Wire which can be shared across many Logics that are connected to each other. This has two big benefits:

Related Issue(s)

Helps mitigate #194

Testing

  • Added new tests where corner cases could have been introduced around combinational logic propagation and edge listening.
  • Ran the (limited) existing benchmark suite and observed slight performance improvement. The existing pipeline benchmark is not sufficient probably to show the true benefit for larger designs, though.

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

Sort of, posedge and negedge will now throw an Exception if the width is not 1.

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

No

@eric-norige
Copy link
Contributor

This refactor seems good to me. Is there any measurement on sim performance speed improvement? Do we need a benchmark suite of designs and stimulus to simulate to identify progress/regressions on simulation performance?

@mkorbel1
Copy link
Contributor Author

mkorbel1 commented Nov 23, 2022

Is there any measurement on sim performance speed improvement?

The one benchmark that's currently in the repo showed some modest relative improvement in simulation performance, but it's not a very meaningful measurement or dramatic difference.

Do we need a benchmark suite of designs and stimulus to simulate to identify progress/regressions on simulation performance?

Yes! I don't have them available and haven't had time to develop them, though. If you (or anyone else) is interested in developing some or contributing existing things that could be reused as benchmarks it would be greatly valuable!

And thank you for taking a look!

@mkorbel1 mkorbel1 merged commit 194a3ae into intel:main Dec 1, 2022
@mkorbel1 mkorbel1 deleted the stackoverflow2 branch December 1, 2022 18:00
quekyj pushed a commit to quekyj/rohd that referenced this pull request Jan 9, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants