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More module and signal naming improvements #440

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merged 2 commits into from
Nov 29, 2023
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@mkorbel1 mkorbel1 commented Nov 28, 2023

Description & Motivation

This PR fixes some more naming issues discovered during customer testing after #439.

  • Make internal signals use an ordered Set to avoid improper duplication of generated SV module definitions.
  • Make Port mergeable to avoid calls to connectIO from duplicating signal names in generated SV unnecessarily.
  • Prevent reserveDefinitionName Modules from being merged if they have different definitionNames.
  • Disable link validation in dart doc for documentation deployment due to dartdoc bug (Documentation for functions in enums are linked but not generated dart-lang/dartdoc#3584).
  • Update doc link to icarus verilog

Related Issue(s)

Fix #345

Testing

Added tests to fix bugs and cover new functionality.

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No, though generated SV will change

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

No

@mkorbel1 mkorbel1 changed the title More naming fixes More module and signal naming improvements Nov 29, 2023
@mkorbel1 mkorbel1 merged commit b02beda into intel:main Nov 29, 2023
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@mkorbel1 mkorbel1 deleted the naming2 branch November 29, 2023 20:23
mjayasim9 pushed a commit to mjayasim9/rohd that referenced this pull request Dec 1, 2023
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