Allow constant Z driving to show up in SV without error

[mkorbel1]

Description & Motivation

Sometimes one may wish to explicitly drive a Z (floating) on a signal and have that show up in the generated SystemVerilog (e.g. testbench or behavioral code). There was an assertion in the SV generation to prevent an accidental z from showing up on a floating signal (left undriven). However, if someone explicitly connects a signal to Const('z') (for example) in a way that can't be collapsed away (e.g. in a mux), we should just generate with the Z in there rather than fail with an assertion. This does not guarantee that every Z in the ROHD side will show up as a Z in the SV side, it just enables explicit floating.

Related Issue(s)

N/A

Testing

Added a couple tests reproducing issues as reported by a user

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

No