Adding mechanisms to remove redundant parentheses. #586
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Description & Motivation
There are cases where generated SystemVerilog code has too many parentheses to increase safety, ensure order of operations and matching the generated intent. This changes add mechanisms to identify redundancies with parenthesis and remove them to simplify the generated code.
Related Issue(s)
#552
Testing
A unit testing script was created to validate the [RedundancyHandler] functionality.
rohd/test/redundancy_handler_test.dart
Backwards-compatibility
No.
Documentation
The [RedundancyHandler] class was added with its code documentation, no need to add more.
rohd/lib/src/utilities/redundancy_handler.dart