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Adding mechanisms to remove redundant parentheses. #586

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Description & Motivation

There are cases where generated SystemVerilog code has too many parentheses to increase safety, ensure order of operations and matching the generated intent. This changes add mechanisms to identify redundancies with parenthesis and remove them to simplify the generated code.

Related Issue(s)

#552

Testing

A unit testing script was created to validate the [RedundancyHandler] functionality.
rohd/test/redundancy_handler_test.dart

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No.

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

The [RedundancyHandler] class was added with its code documentation, no need to add more.
rohd/lib/src/utilities/redundancy_handler.dart

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@mkorbel1 mkorbel1 left a comment

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Similar comments as #584, will review in more detail soon when I can

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See notes in #584 (review), which applies to this PR as well

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