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Pull requests: intel/rohd

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Pull requests list

SystemVerilog block labels
#585 opened Mar 8, 2025 by lucasphillips updated Mar 20, 2025
1
11
Add docs about trusting ROHD for development
#589 opened Mar 18, 2025 by mkorbel1 updated Mar 18, 2025
Adding mechanisms to remove redundant parentheses.
#586 opened Mar 8, 2025 by gus-bonilla-86 • Changes requested updated Mar 10, 2025
2
Adding mechanisms to avoid unnecessary swizzle conversions.
#584 opened Mar 8, 2025 by gus-bonilla-86 • Changes requested updated Mar 10, 2025
1
2
Avoid Module creation for Constant Gate scenarios
#481 opened Apr 5, 2024 by mjayasim9 • Changes requested updated Jan 31, 2025
1
10
Vscode extension
#437 opened Nov 14, 2023 by quekyj • Changes requested updated May 9, 2024
18
[WIP] Add local Markdown checks
#330 opened Mar 22, 2023 by chykon • Draft updated Mar 22, 2023
Automatically check for new Dart lints
#284 opened Feb 24, 2023 by chykon • Draft updated Feb 26, 2023
2
Fix bug related to clock divider simulation, fix #191
#192 opened Nov 1, 2022 by mkorbel1 • Draft updated Nov 23, 2022
1
3
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