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PCIe: add flit_mode_disable configuration
fix #318 Signed-off-by: Aaron Li <aaron.li@intel.com>
1 parent 24fa716 commit 92fda15

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6 files changed

+314
-9
lines changed

6 files changed

+314
-9
lines changed

doc/ide_test_ini.md

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Original file line numberDiff line numberDiff line change
@@ -87,6 +87,7 @@ Settings of **Topology** / **Configuration** / **TestSuite** are different.
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|aggregation|0/1|0|O||
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|selective_ide_for_configuration|0/1|0|O||
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|tee_limited_stream|0/1|0|O||
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|flit_mode_disable|0/1|0|O||
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[TestSuite_x]
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|Entry|Value|Default|Mandatory|Comment|

teeio-validator/include/ide_test.h

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@@ -1,6 +1,6 @@
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/**
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* Copyright Notice:
3-
* Copyright 2023-2024 Intel. All rights reserved.
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* Copyright 2023-2025 Intel. All rights reserved.
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* License: BSD 3-Clause License.
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**/
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@@ -267,6 +267,7 @@ typedef enum {
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IDE_TEST_CONFIGURATION_TYPE_AGGGEG,
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IDE_TEST_CONFIGURATION_TYPE_SELECTIVE_IDE_FOR_CONFIG,
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IDE_TEST_CONFIGURATION_TYPE_TEE_LIMITED_STREAM,
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IDE_TEST_CONFIGURATION_TYPE_FLIT_MODE_DISABLE,
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IDE_TEST_CONFIGURATION_TYPE_NUM
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} IDE_TEST_CONFIGURATION_TYPE;
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@@ -279,21 +280,24 @@ typedef enum {
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_PCRC)) | \
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_AGGGEG)) | \
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_SELECTIVE_IDE_FOR_CONFIG)) | \
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_TEE_LIMITED_STREAM)))
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_TEE_LIMITED_STREAM)) | \
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_FLIT_MODE_DISABLE)))
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#define LINK_IDE_CONFIGURATION_BITMASK \
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((BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_DEFAULT)) | \
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_SWITCH)) | \
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_PARTIAL_HEADER_ENC)) | \
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_PCRC)) | \
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_AGGGEG)))
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_AGGGEG)) | \
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_FLIT_MODE_DISABLE)))
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#define SELECTIVE_LINK_IDE_CONFIGURATION_BITMASK \
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((BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_DEFAULT)) | \
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_PARTIAL_HEADER_ENC)) | \
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_PCRC)) | \
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_SELECTIVE_IDE_FOR_CONFIG)) | \
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_AGGGEG)))
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_AGGGEG)) | \
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(BIT_MASK(IDE_TEST_CONFIGURATION_TYPE_FLIT_MODE_DISABLE)))
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typedef enum {
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IDE_COMMON_TEST_ACTION_RUN = 0,

teeio-validator/library/pcie_ide_test_lib/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@ SET(src_pcie_ide_test_lib
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test_config/test_config_pcrc.c
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test_config/test_config_default.c
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test_config/test_config_sel_ide_for_cfg_req.c
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test_config/test_config_flit_mode_disable.c
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## test groups
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test_group/test_group.c
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)

teeio-validator/library/pcie_ide_test_lib/include/pcie_ide_common.h

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
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/**
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* Copyright Notice:
3-
* Copyright 2024 Intel. All rights reserved.
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* Copyright 2024-2025 Intel. All rights reserved.
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* License: BSD 3-Clause License.
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**/
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@@ -148,6 +148,21 @@ bool pcie_ide_test_config_disable_sel_ide_for_cfg_req(void *test_context);
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bool pcie_ide_test_config_support_sel_ide_for_cfg_req(void *test_context);
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bool pcie_ide_test_config_check_sel_ide_for_cfg_req(void *test_context);
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// flit mode disable
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bool pcie_ide_test_config_flit_mode_disable_enable_sel(void *test_context);
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bool pcie_ide_test_config_flit_mode_disable_disable_sel(void *test_context);
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bool pcie_ide_test_config_flit_mode_disable_support_sel(void *test_context);
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bool pcie_ide_test_config_flit_mode_disable_check_sel(void *test_context);
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bool pcie_ide_test_config_flit_mode_disable_enable_link(void *test_context);
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bool pcie_ide_test_config_flit_mode_disable_disable_link(void *test_context);
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bool pcie_ide_test_config_flit_mode_disable_support_link(void *test_context);
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bool pcie_ide_test_config_flit_mode_disable_check_link(void *test_context);
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162+
bool pcie_ide_test_config_flit_mode_disable_enable_sel_link(void *test_context);
163+
bool pcie_ide_test_config_flit_mode_disable_disable_sel_link(void *test_context);
164+
bool pcie_ide_test_config_flit_mode_disable_support_sel_link(void *test_context);
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bool pcie_ide_test_config_flit_mode_disable_check_sel_link(void *test_context);
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//
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// PCIE_IDE Test Group
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//

teeio-validator/library/pcie_ide_test_lib/pcie_ide_common.c

Lines changed: 23 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/**
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* Copyright Notice:
3-
* Copyright 2023-2024 Intel. All rights reserved.
3+
* Copyright 2023-2025 Intel. All rights reserved.
44
* License: BSD 3-Clause License.
55
**/
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@@ -20,6 +20,7 @@ const char* m_ide_test_configuration_name[] = {
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"aggregation",
2121
"selective_ide_for_configuration",
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"tee_limited_stream",
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"flit_mode_disable",
2324
NULL
2425
};
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@@ -52,7 +53,13 @@ ide_test_config_funcs_t m_config_funcs[IDE_TEST_TOPOLOGY_TYPE_NUM][IDE_TEST_CONF
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pcie_ide_test_config_support_sel_ide_for_cfg_req,
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pcie_ide_test_config_check_sel_ide_for_cfg_req
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},
55-
{NULL, NULL, NULL, NULL} // tee_limited_stream
56+
{NULL, NULL, NULL, NULL}, // tee_limited_stream
57+
{ // flit mode disable
58+
pcie_ide_test_config_flit_mode_disable_enable_sel,
59+
pcie_ide_test_config_flit_mode_disable_disable_sel,
60+
pcie_ide_test_config_flit_mode_disable_support_sel,
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pcie_ide_test_config_flit_mode_disable_check_sel
62+
},
5663
},
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{ // link_ide
5865
{
@@ -76,7 +83,13 @@ ide_test_config_funcs_t m_config_funcs[IDE_TEST_TOPOLOGY_TYPE_NUM][IDE_TEST_CONF
7683

7784
{NULL, NULL, NULL, NULL},
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{NULL, NULL, NULL, NULL},
79-
{NULL, NULL, NULL, NULL}
86+
{NULL, NULL, NULL, NULL},
87+
{ // flit mode disable
88+
pcie_ide_test_config_flit_mode_disable_enable_link,
89+
pcie_ide_test_config_flit_mode_disable_disable_link,
90+
pcie_ide_test_config_flit_mode_disable_support_link,
91+
pcie_ide_test_config_flit_mode_disable_check_link
92+
},
8093
},
8194
{ // selective_and_link_ide
8295
{
@@ -97,7 +110,13 @@ ide_test_config_funcs_t m_config_funcs[IDE_TEST_TOPOLOGY_TYPE_NUM][IDE_TEST_CONF
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},
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{NULL, NULL, NULL, NULL},
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{NULL, NULL, NULL, NULL},
100-
{NULL, NULL, NULL, NULL}
113+
{NULL, NULL, NULL, NULL},
114+
{ // flit mode disable
115+
pcie_ide_test_config_flit_mode_disable_enable_sel_link,
116+
pcie_ide_test_config_flit_mode_disable_disable_sel_link,
117+
pcie_ide_test_config_flit_mode_disable_support_sel_link,
118+
pcie_ide_test_config_flit_mode_disable_check_sel_link
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},
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}
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};
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