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AMD XOP: VGPRy_R, VGPRy_B. Use VGPR32_[RB] for correct modal behavior.
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  * needed to ignore upper 8 regs when in 32b mode.

  * use VGPR32_B and VGPR32_R for correct 32b mode behavior of AMD XOP
    instr.

  * Add&use VGPRy_R and VGPRy_B for correct 32/64b mode behavior of
    AMD XOP.

  * #233

(cherry picked from commit 1dd63ff3cf987057016ca354f10facb206fec102)
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@mjcharne @markcharney
mjcharne authored and markcharney committed Nov 3, 2020
1 parent b263f4a commit d1d9ad3
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Showing 2 changed files with 38 additions and 27 deletions.
52 changes: 26 additions & 26 deletions datafiles/amd/amdxop/amd-xop-isa.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -992,14 +992,14 @@ ATTRIBUTES: AMDONLY
FLAGS: MUST [ cf-0 pf-u af-u zf-mod sf-u of-0 ]

PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()
OPERANDS: REG0=GPR32_R():w:d MEM0:r:d IMM0:r:d
OPERANDS: REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:d
PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()
OPERANDS: REG0=GPRy_R():w:y MEM0:r:y IMM0:r:d
OPERANDS: REG0=VGPRy_R():w:y MEM0:r:y IMM0:r:d

PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()
OPERANDS: REG0=GPR32_R():w:d REG1=GPR32_B():r:d IMM0:r:d
OPERANDS: REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:d
PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()
OPERANDS: REG0=GPRy_R():w:y REG1=GPRy_B():r:y IMM0:r:d
OPERANDS: REG0=VGPRy_R():w:y REG1=VGPRy_B():r:y IMM0:r:d
}

{
Expand All @@ -1018,9 +1018,9 @@ PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MOD
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
}

{
Expand All @@ -1039,9 +1039,9 @@ PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MOD
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
}

{
Expand All @@ -1060,9 +1060,9 @@ PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MOD
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
}

{
Expand All @@ -1081,9 +1081,9 @@ PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MOD
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
}

{
Expand All @@ -1102,9 +1102,9 @@ PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MOD
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
}

{
Expand All @@ -1123,9 +1123,9 @@ PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MOD
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
}

{
Expand All @@ -1144,9 +1144,9 @@ PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MOD
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
}

{
Expand All @@ -1165,9 +1165,9 @@ PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MOD
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
}

{
Expand All @@ -1186,9 +1186,9 @@ PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MOD
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y

PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
}

{
Expand All @@ -1200,7 +1200,7 @@ EXTENSION: XOP
ATTRIBUTES: AMDONLY

PATTERN: XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS: REG0=GPRy_B():w:y
OPERANDS: REG0=VGPRy_B():w:y
}

{
Expand All @@ -1212,7 +1212,7 @@ EXTENSION: XOP
ATTRIBUTES: AMDONLY

PATTERN: XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
OPERANDS: REG0=GPRy_B():w:y
OPERANDS: REG0=VGPRy_B():w:y
}

{
Expand All @@ -1229,7 +1229,7 @@ PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() U
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d

PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM32()
OPERANDS: REG0=VGPRy_N():w:y REG1=GPR32_B():r:y IMM0:r:d
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPR32_B():r:y IMM0:r:d
}

{
Expand All @@ -1244,5 +1244,5 @@ PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UI
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d

PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM32()
OPERANDS: REG0=VGPRy_N():w:y REG1=GPR32_B():r:y IMM0:r:d
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPR32_B():r:y IMM0:r:d
}
13 changes: 12 additions & 1 deletion datafiles/hswbmi/hsw-reg-table.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,18 @@
#
#END_LEGAL

# VGPRy_N is used by AMD XOP only but the lower level stuff is used by HSW NI
# VGPRy_N, VGPRy_B, and VGPRy_R are used by AMD XOP.
# Only but the lower level stuff is used by HSW NI.

xed_reg_enum_t VGPRy_R()::
EOSZ=1 | OUTREG=VGPR32_R()
EOSZ=2 | OUTREG=VGPR32_R()
EOSZ=3 | OUTREG=VGPR64_R()

xed_reg_enum_t VGPRy_B()::
EOSZ=1 | OUTREG=VGPR32_B()
EOSZ=2 | OUTREG=VGPR32_B()
EOSZ=3 | OUTREG=VGPR64_B()

xed_reg_enum_t VGPRy_N()::
EOSZ=1 | OUTREG=VGPR32_N()
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