riscv-sv

WIP SystemVerilog RISC-V core

A SystemVerilog implementation of a RISC-V core, not quite working yet!

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
asm		asm
hex		hex
ALU.sv		ALU.sv
ALUBench.sv		ALUBench.sv
Mem.sv		Mem.sv
PC.sv		PC.sv
PCBench.sv		PCBench.sv
Pipeline.sv		Pipeline.sv
README.md		README.md
Regs.sv		Regs.sv
RegsBench.sv		RegsBench.sv
Sys.sv		Sys.sv
Top.sv		Top.sv
TopBench.sv		TopBench.sv
home.nix		home.nix
mod_top_tb.vcd		mod_top_tb.vcd
shell.nix		shell.nix
sim.sh		sim.sh