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js4ngu/readme.md

πŸ‘·πŸ»β€β™‚οΈ Hardware Engineer Jongsang's Github

  • My GitHub stats
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  • πŸ™‹πŸ»β€β™‚οΈ Hi, I'm "Jongsang Yoo"
  • πŸ‘¨πŸ»β€πŸŽ“ Now, I'm studying Computer Science & Engineering (M.S. student) in Korea Univ.
  • πŸ‘¨πŸ»β€πŸŽ“ I majored Eelctronic Engineering (B.S. degree) in Myoungji Univ.
  • πŸ”¬ I'm currently focused on "microprocessor architecture (RISC-V), custom vector ISAs for LLM acceleration, and SoC architecture".
  • πŸ”¬ I have also researched "NTT-based hardware accelerators (targeting ZKP, FHE, PQC, etc.) using systolic array".


πŸ“š Skill Stack

  • C / Python
  • STM32 / IAR
  • FPGA : Xylinx - Verilog / Vivado, Vitis
  • FPGA : Altera - Verilog / Quartus II
  • Atmega / Atmel Studio
  • Inventor, Fusion360
  • Kicad
  • PSIM

Popular repositories Loading

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  2. SoC_2022_MJU SoC_2022_MJU Public

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  3. EMsys_2021_MJU EMsys_2021_MJU Public

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  6. ECE743-GEMM-Chissel ECE743-GEMM-Chissel Public

    [κ³ λ €λŒ€ ECE743] Hardware Accelerators for GEMM with Chisel - Midterm Project

    Scala 1