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Merge pull request #2 from kasper201/UartSecondDirection
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Uart second direction
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@PineAppleOnTV
PineAppleOnTV authored Mar 10, 2024
2 parents 5dad9a0 + 0161260 commit 6ece903
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Showing 78 changed files with 2,803 additions and 1,988 deletions.
19 changes: 19 additions & 0 deletions STM32/TestBenchForFPGA/boards/nucleo_f030r8.overlay
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&usart1{
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <230400>;
status = "okay";
};

&usart2{
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};

/ {
aliases {
usart = &usart1;
};
};
7 changes: 7 additions & 0 deletions STM32/TestBenchForFPGA/boards/nucleo_f091rc.overlay
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Expand Up @@ -5,6 +5,13 @@
status = "okay";
};

&usart2{
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};

/ {
aliases {
usart = &usart1;
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3 changes: 0 additions & 3 deletions STM32/TestBenchForFPGA/src/main.c
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Expand Up @@ -16,7 +16,6 @@
#include <string.h>

#include "uart.h"
#include "compc.h"
#include "main.h"

#define SLEEP_TIME_MS 10
Expand Down Expand Up @@ -152,8 +151,6 @@ int main(void)
}
}

readPc(); // Reads uart output from the FPGA

k_msleep(SLEEP_TIME_MS);
}
}
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4 changes: 2 additions & 2 deletions VHDL/uart_communication/uart_communication.cache/wt/project.wpc
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version:1
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8 changes: 4 additions & 4 deletions VHDL/uart_communication/uart_communication.cache/wt/synthesis.wdf
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4 changes: 2 additions & 2 deletions VHDL/uart_communication/uart_communication.cache/wt/webtalk_pa.xml
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Expand Up @@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Fri Feb 2 17:01:38 2024">
<application name="pa" timeStamp="Mon Feb 26 00:48:07 2024">
<section name="Project Information" visible="false">
<property name="ProjectID" value="991ff43018104df7b3345545a9203d50" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
<property name="ProjectIteration" value="4" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
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14 changes: 14 additions & 0 deletions VHDL/uart_communication/uart_communication.runs/.jobs/vrs_config_2.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/Wouter/Desktop/School/Projecten/RetroGame/RetroGame/VHDL/uart_communication/uart_communication.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/Wouter/Desktop/School/Projecten/RetroGame/RetroGame/VHDL/uart_communication/uart_communication.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
</Parameters>
<ProductInfo Name="vivado"/>
</Runs>

14 changes: 14 additions & 0 deletions VHDL/uart_communication/uart_communication.runs/.jobs/vrs_config_3.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/Wouter/Desktop/School/Projecten/RetroGame/RetroGame/VHDL/uart_communication/uart_communication.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/Wouter/Desktop/School/Projecten/RetroGame/RetroGame/VHDL/uart_communication/uart_communication.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
</Parameters>
<ProductInfo Name="vivado"/>
</Runs>

14 changes: 14 additions & 0 deletions VHDL/uart_communication/uart_communication.runs/.jobs/vrs_config_4.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/Wouter/Desktop/School/Projecten/RetroGame/RetroGame/VHDL/uart_communication/uart_communication.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="C:/Users/Wouter/Desktop/School/Projecten/RetroGame/RetroGame/VHDL/uart_communication/uart_communication.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
</Parameters>
<ProductInfo Name="vivado"/>
</Runs>

2 changes: 1 addition & 1 deletion VHDL/uart_communication/uart_communication.runs/impl_1/.init_design.begin.rst
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="Wouter" Host="PC-WOUTERROSENB" Pid="26048">
<Process Command=".planAhead." Owner="Wouter" Host="PC-WOUTERROSENB" Pid="24040">
</Process>
</ProcessHandle>
2 changes: 1 addition & 1 deletion VHDL/uart_communication/uart_communication.runs/impl_1/.opt_design.begin.rst
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="Wouter" Host="PC-WOUTERROSENB" Pid="26048">
<Process Command=".planAhead." Owner="Wouter" Host="PC-WOUTERROSENB" Pid="24040">
</Process>
</ProcessHandle>
2 changes: 1 addition & 1 deletion VHDL/uart_communication/uart_communication.runs/impl_1/.phys_opt_design.begin.rst
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="Wouter" Host="PC-WOUTERROSENB" Pid="26048">
<Process Command=".planAhead." Owner="Wouter" Host="PC-WOUTERROSENB" Pid="24040">
</Process>
</ProcessHandle>
2 changes: 1 addition & 1 deletion VHDL/uart_communication/uart_communication.runs/impl_1/.place_design.begin.rst
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@@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="Wouter" Host="PC-WOUTERROSENB" Pid="26048">
<Process Command=".planAhead." Owner="Wouter" Host="PC-WOUTERROSENB" Pid="24040">
</Process>
</ProcessHandle>
2 changes: 1 addition & 1 deletion VHDL/uart_communication/uart_communication.runs/impl_1/.route_design.begin.rst
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="Wouter" Host="PC-WOUTERROSENB" Pid="26048">
<Process Command=".planAhead." Owner="Wouter" Host="PC-WOUTERROSENB" Pid="24040">
</Process>
</ProcessHandle>
2 changes: 1 addition & 1 deletion VHDL/uart_communication/uart_communication.runs/impl_1/.vivado.begin.rst
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="Wouter" Host="PC-WOUTERROSENB" Pid="41788" HostCore="16" HostMemory="034281848832">
<Process Command="vivado.bat" Owner="Wouter" Host="PC-WOUTERROSENB" Pid="25628" HostCore="16" HostMemory="034281848832">
</Process>
</ProcessHandle>
2 changes: 1 addition & 1 deletion VHDL/uart_communication/uart_communication.runs/impl_1/.write_bitstream.begin.rst
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="Wouter" Host="PC-WOUTERROSENB" Pid="26048">
<Process Command=".planAhead." Owner="Wouter" Host="PC-WOUTERROSENB" Pid="24040">
</Process>
</ProcessHandle>
2 changes: 1 addition & 1 deletion VHDL/uart_communication/uart_communication.runs/impl_1/clockInfo.txt
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-------------------------------------
| Tool Version : Vivado v.2023.2
| Date : Fri Feb 2 17:02:43 2024
| Date : Mon Feb 26 00:49:14 2024
| Host : PC-WouterRosenbrand
| Design : design_1
| Device : xc7a35t-cpg236-1--
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20 changes: 16 additions & 4 deletions VHDL/uart_communication/uart_communication.runs/impl_1/gen_run.xml
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<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1706889698">
<GenRun Id="impl_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1708904887">
<File Type="ROUTE-PWR" Name="main_power_routed.rpt"/>
<File Type="PA-TCL" Name="main.tcl"/>
<File Type="ROUTE-PWR-SUM" Name="main_power_summary_routed.pb"/>
Expand Down Expand Up @@ -92,6 +92,12 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/TX_Send.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/UART_TX.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
Expand Down Expand Up @@ -130,14 +136,20 @@
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<File Path="$PSRCDIR/utils_1/imports/synth_1/main.dcp">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedInSteps" Val="synth_1"/>
<Attr Name="AutoDcp" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
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4 changes: 0 additions & 4 deletions VHDL/uart_communication/uart_communication.runs/impl_1/main.tcl
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Expand Up @@ -115,18 +115,14 @@ proc step_failed { step } {
OPTRACE "impl_1" END { }
}

set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000

OPTRACE "impl_1" START { ROLLUP_1 }
OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param checkpoint.writeSynthRtdsInDcp 1
set_param chipscope.maxJobs 4
set_param synth.incrementalSynthesisCache C:/Users/Wouter/Desktop/School/Projecten/RetroGame/RetroGame/VHDL/uart_communication/.Xil/Vivado-26744-PC-WouterRosenbrand/incrSyn
set_param runs.launchOptions { -jobs 16 }
OPTRACE "create in-memory project" START { }
create_project -in_memory -part xc7a35tcpg236-1
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