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Updating to embedded-hal
v1.0
#61
Conversation
LGTM except the removal of the pub struct MyControllerState {
spi: SpiBus<...>,
cs_w5500: OutputPin<..>,
cs_ds93c46: OutputPin<...>,
w5500_state: InactiveDevice<w5500::Manual>,
ds93c46_state: DS93C46<..>,
}
impl MyControllerState {
pub fn new(...) -> Self { ... }
pub fn send_udp(&mut self, destination: SocketAddr, data: &[u8]) -> Result<...> {
let mut device = self.w5500_state.activate_ref(FourWireRef::new(&mut self.spi, &mut self.cs_w5500))?;
let mut socket = device.socket().unwrap(); // for simplicity of this example, this socket is not cached in MyControllerState
device.connect(&mut socket, destination).unwrap(); // for simplicity of this example...
nb::block!(device.send(socket, data))
}
pub fn write_eeprom(&mut self, position: usize, data: &[u8], delay: impl DelayMs<u16>) -> Result<...> {
self.ds93c46_state.enable_write(spi, delay)?;
let result = self.ds93c46_state.write(spi, delay, position, data);
self.ds93c46_state.disable_write(spi, delay)?;
result
}
} In this example, the SPI bus is shared between the w5500 chip and an eeprom:
How would that look with the |
That would look (roughly) like: // Instantiate the SPI peripheral
let bus = hal::spi::new();
let w5500_csn = hal::gpio::get();
let eeprom_csn = hal::gpio::get();
// Store the SPI bus somewhere that all of your users can access it. In this case, assume we're using SPI always in the same context (i.e. same interrupt priority level)
let bus_refcell = core::cell::RefCell::new(bus);
// Construct the EEPROM and W5500, each of which get their own owned handles to the bus + CS pins.
let w5500_spi = embedded_hal_bus::spi::RefCellDevice::new(&bus_refcell, w5500_csn);
let w5500 = w5500::UninitializedDevice::new(w5500::bus::FourWire(w5500_spi)).initialize().unwrap();
let eeprom_spi = embedded_hal_bus::spi::RefCellDevice::new(&bus_refcell, eeprom_csn);
let eeprom = Eeprom::new(eeprom_spi);
// Now freely use the EEPROM and W5500 You can use different types of storage for the actual bus depending on your application requirements (i.e. Mutex-based, Atomic-access based if you're using RTIC, or a critical-section protected bus). https://docs.rs/embedded-hal-bus/latest/embedded_hal_bus/spi/index.html has all of the supported bus synchronization types currently. The synchronization type (i.e. |
Also, I want to point out that the
|
I'd also be happy to reinstate |
Sorry, I am currently at work and cannot look into this in detail until later. I support the idea to keep at least |
No worries, I've reintroduced the |
Sorry, I should have been more verbose with my earlier response. There is still the need for the Regarding your earlier points
This isn't true, because only references are passed around. The If you have the spare time, it might be useful to add one or two sentences to the Sorry to bother you so much with this and thank you. |
@kellerkindt I proposed a new approach to provide an equivalent of |
Thanks for the discussion and review! :) |
This PR refactors the driver to use the 1.0 release of the
embedded-hal
.Because of
embedded-hal-bus
being available to provide for SPI buses with multiple peripherals, theRef
implementations have been removed entirely because this crate doesn't need to worry about sharing the SPI bus across multiple owners any longer.