Vectorised instructions for S2?

[marklit]

I've noticed S2 uses 47 unique opcodes in encodeblock_amd64.s but none are vectorised. Are there any plans to support AVX2 or Intel's other vectorisation opcode sets in the future?

[klauspost]

I have not found any useful SIMD instructions for compression.

There is a single interesting BMI instruction which is 1 cycle faster on AMD Zen1-3. It is enabled at compile time by setting GOAMD64=v3 env var.

Didn't see significant enough speedup to duplicate all code for it. On most Intel CPUs and Zen4 they are equal anyway.

[marklit]

Okay, thank you.

[alexey-milovidov]

But vector instructions are useful for decompression.
See https://github.com/ClickHouse/ClickHouse/blob/master/src/Compression/LZ4_decompress_faster.cpp in ClickHouse.

[klauspost]

The current code expands writes to 8 bytes, even with small offsets.

The case for calling "verySlowForwardCopy" will be the same, since your vector writes needs to respect the end of the destination.

You are of course welcome to send a PR.