riscv32 support for panic-probe

knurling-rs · Nov 24, 2023 · f0f3a43 · f0f3a43
1 parent 7a31dfb
commit f0f3a43
Show file tree

Hide file tree

Showing 2 changed files with 39 additions and 15 deletions.
diff --git a/firmware/panic-probe/Cargo.toml b/firmware/panic-probe/Cargo.toml
@@ -11,10 +11,16 @@ repository = "https://github.com/knurling-rs/defmt"
 version = "0.3.1"
 
 [dependencies]
-cortex-m = "0.7"
 defmt = { version = "0.3", path = "../../defmt", optional = true }
 rtt-target = { version = "0.4", optional = true }
 
+[target.'cfg(target_arch = "arm")'.dependencies]
+cortex-m = "0.7"
+
+[target.'cfg(target_arch = "riscv32")'.dependencies]
+semihosting = "0.1.4"
+riscv = "0.10.1"
+
 
 [features]
 # Print the panic message using `rtt-target`.

diff --git a/firmware/panic-probe/src/lib.rs b/firmware/panic-probe/src/lib.rs
@@ -20,8 +20,8 @@
 #![cfg(target_os = "none")]
 #![doc(html_logo_url = "https://knurling.ferrous-systems.com/knurling_logo_light_text.svg")]
 
-#[cfg(not(cortex_m))]
-compile_error!("`panic-probe` only supports Cortex-M targets (thumbvN-none-eabi[hf])");
+#[cfg(all(not(cortex_m), not(target_arch = "riscv32")))]
+compile_error!("`panic-probe` only supports Cortex-M targets (thumbvN-none-eabi[hf]) or riscv32");
 
 // Functionality `cfg`d out on platforms with OS/libstd.
 #[cfg(target_os = "none")]
@@ -42,7 +42,7 @@ mod imp {
     fn panic(info: &PanicInfo) -> ! {
         static PANICKED: AtomicBool = AtomicBool::new(false);
 
-        cortex_m::interrupt::disable();
+        crate::disable_isr();
 
         // Guard against infinite recursion, just in case.
         if !PANICKED.load(Ordering::Relaxed) {
@@ -69,21 +69,39 @@ mod imp {
 /// ```
 #[cfg(target_os = "none")]
 pub fn hard_fault() -> ! {
-    // If `UsageFault` is enabled, we disable that first, since otherwise `udf` will cause that
-    // exception instead of `HardFault`.
-    #[cfg(not(any(armv6m, armv8m_base)))]
+    #[cfg(cortex_m)]
     {
-        const SHCSR: *mut u32 = 0xE000ED24usize as _;
-        const USGFAULTENA: usize = 18;
-
-        unsafe {
-            let mut shcsr = core::ptr::read_volatile(SHCSR);
-            shcsr &= !(1 << USGFAULTENA);
-            core::ptr::write_volatile(SHCSR, shcsr);
+        // If `UsageFault` is enabled, we disable that first, since otherwise `udf` will cause that
+        // exception instead of `HardFault`.
+        #[cfg(not(any(armv6m, armv8m_base)))]
+        {
+            const SHCSR: *mut u32 = 0xE000ED24usize as _;
+            const USGFAULTENA: usize = 18;
+
+            unsafe {
+                let mut shcsr = core::ptr::read_volatile(SHCSR);
+                shcsr &= !(1 << USGFAULTENA);
+                core::ptr::write_volatile(SHCSR, shcsr);
+            }
         }
+
+        cortex_m::asm::udf();
     }
 
-    cortex_m::asm::udf();
+    #[cfg(target_arch = "riscv32")]
+    {
+        semihosting::process::abort();
+    }
+}
+
+#[cfg(target_os = "none")]
+pub fn disable_isr() {
+    #[cfg(cortex_m)]
+    cortex_m::interrupt::disable();
+    #[cfg(target_arch = "riscv32")]
+    unsafe {
+        riscv::interrupt::disable()
+    };
 }
 
 #[cfg(feature = "print-rtt")]