Merge pull request #21 from kosarev/undoc_bit_fix

Fixed undocumented BIT instructions

tests/tests_z80

@@ -185,6 +185,54 @@ fdcb014e bit 1, (iy + 1)
 20 set_index_rp iy -> hl
 20 done
 
+# Undocumented BIT
+ddcb0440 bit 0, (ix + 4)
+ 0 m1_fetch
+ 0   fetch dd at 0000
+ 0     get_pc_on_fetch 0000
+ 0     set_addr_bus 0000 -> 0000
+ 2     mreq_wait 0000
+ 2     get_ir_on_refresh 0000
+ 2     set_addr_bus 0000 -> 0000
+ 4     set_pc_on_fetch 0000 -> 0001
+ 4   set_r 00 -> 01
+ 4 set_index_rp hl -> ix
+ 4 disable_int
+ 4 m1_fetch
+ 4   fetch cb at 0001
+ 4     get_pc_on_fetch 0001
+ 4     set_addr_bus 0000 -> 0001
+ 6     mreq_wait 0001
+ 6     get_ir_on_refresh 0001
+ 6     set_addr_bus 0001 -> 0001
+ 8     set_pc_on_fetch 0001 -> 0002
+ 8   set_r 01 -> 02
+ 8 disp_read 04 at 0002
+ 8   get_pc_on_disp_read 0002
+ 8   read 04 at 0002
+ 8     set_addr_bus 0001 -> 0002
+10     mreq_wait 0002
+11   set_pc_on_disp_read 0002 -> 0003
+11 fetch 40 at 0003
+11   get_pc_on_fetch 0003
+11   set_addr_bus 0002 -> 0003
+13   mreq_wait 0003
+13   get_ir_on_refresh 0002
+13   set_addr_bus 0003 -> 0002
+15   set_pc_on_fetch 0003 -> 0004
+15 fetch_cycle_extra_1t
+16 get_ixl 00
+16 get_ixh 00
+16 read 00 at 0004
+16   set_addr_bus 0002 -> 0004
+18   mreq_wait 0004
+19 read_cycle_extra_1t
+20 set_wz 0000 -> 0004
+20 get_f 00
+20 set_f 00 -> 54
+20 set_index_rp ix -> hl
+20 done
+
 # CALL nn
 cddf0e call 0x0edf
  0 m1_fetch

z80.h

@@ -1625,7 +1625,8 @@ class z80_disasm
         self().on_format("T", k); }
     void on_bit(unsigned b, reg r, fast_u8 d) {
         iregp irp = self().on_get_iregp_kind();
-        self().on_format("bit U, R", b, r, irp, d); }
+        reg access_r = irp == iregp::hl ? r : reg::at_hl;
+        self().on_format("bit U, R", b, access_r, irp, d); }
     void on_call_cc_nn(condition cc, fast_u16 nn) {
         self().on_format("call C, W", cc, nn); }
     void on_ccf() {
@@ -3338,12 +3339,13 @@ class z80_executor : public internals::executor_base<B> {
         } }
     void on_bit(unsigned b, reg r, fast_u8 d) {
         iregp irp = self().on_get_iregp_kind();
-        fast_u8 v = self().on_get_reg(r, irp, d, /* long_read_cycle= */ true);
+        reg access_r = irp == iregp::hl ? r : reg::at_hl;
+        fast_u8 v = self().on_get_reg(access_r, irp, d, /* long_read_cycle= */ true);
         fast_u8 f = self().on_get_f();
         fast_u8 m = v & (1u << b);
         // TODO: Is it always (m & sf_mask)? Regardless of whether m is zero or not?
         f = (f & cf_mask) | hf_mask | (m ? (m & sf_mask) : (zf_mask | pf_mask));
-        if(!is_hl_iregp() || r == reg::at_hl)
+        if(!is_hl_iregp() || access_r == reg::at_hl)
             v = get_high8(self().on_get_wz());
         f |= v & (xf_mask | yf_mask);
         self().on_set_f(f); }