Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Support IM0 #3

Open
kosarev opened this issue Oct 17, 2020 · 3 comments
Open

Support IM0 #3

kosarev opened this issue Oct 17, 2020 · 3 comments
Assignees
@kosarev
Labels
enhancement

Comments

@kosarev
Copy link
Owner

kosarev commented Oct 17, 2020

Aside of #2, this seems to be the only missing feature.
@kosarev kosarev added the bug label Oct 17, 2020
@kosarev kosarev self-assigned this Oct 17, 2020
@simonowen
Copy link
Collaborator

Rather than asserting, could the default implementation behave as though FF is read from the bus to give RST &38? From what I remember from testing IM 0 and IM 1 behave the same if there's nothing providing an instruction on the bus. The timing might be 6T instead of 7T for ack.

kosarev added a commit that referenced this issue Jun 2, 2021
@kosarev
[#3] Handle IM 0 interrupts as IM 1 ones for now.
9ae1dad
@kosarev
Copy link
Owner Author

kosarev commented Jun 2, 2021

Certainly a good idea. 9ae1dad should implement it. Regarding timings: according to my copy of the Sean Young paper, IM 0 and IM 1 both take 13 ticks, which I understand means we have ack(7) write(3) write(3) here.

@kosarev kosarev added enhancement and removed bug labels Jun 3, 2021
@kosarev
Copy link
Owner Author

kosarev commented Jun 3, 2021

Now that the assert() is removed, this looks more like an enhancement rather than a bug.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees

@kosarev kosarev

Labels
enhancement
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
2 participants
@simonowen @kosarev