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Synthesis
One of tenyr's goals is to be synthesisable on a reasonably-sized FPGA. The concept has been proven with the Verilog implementation found in the hw/ directory, using the Xilinx XC6SLX16 FPGA found on the Digilent Nexys3 development board. The current implementation is an unpipelined, multi-cycle design at eight clocks per instruction, clocked at 80MHz (for a throughput of 10 MIPS). The design can be run up to about 83MHz (limited by the speed of the 32x32-bit multiplier) in my FPGA. Future revisions to tenyr will pursue more sophisticated microarchitectures to avoid limiting the clock speed by a single operation -- the current version of tenyr is intended to be as simple and regular as possible.
The basis of the Verilog implementation is found in hw/verilog/ ; there are directories with code specific to :
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Icarus Verilog simulation ---
hw/icarus/ -
Xilinx ISE synthesis (previously demonstrated, stale) ---
hw/xilinx/ - Lattice synthesis (untested) ---
hw/lattice/ -
VPI ---
hw/vpi/