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Issues: kuznia-rdzeni/coreblocks
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Update documentation after separating Transactron
documentation
Improvements or additions to documentation
#767
opened Dec 2, 2024 by
Hazardu
RISC-V Debug Specification
enhancement
New feature or request
#764
opened Nov 26, 2024 by
piotro888
6 tasks
Instruction tracking debugging interface
enhancement
New feature or request
tests
Tests and testbenches (not infrastructure)
#763
opened Nov 26, 2024 by
piotro888
Check for CRLF line endings in CI formatting runs
infrastructure
CI, testing, etc.
#761
opened Nov 26, 2024 by
piotro888
Accept custom New feature or request
nice to have
Could be useful, but not a top priority
CoreConfiguration
in gen_verilog
script
enhancement
#757
opened Nov 19, 2024 by
piotro888
Pytest option Something isn't working
tests
Tests and testbenches (not infrastructure)
--coreblocks-test-count
is not compatible with -k
bug
#753
opened Nov 13, 2024 by
tilk
Tests for ManyToOneConnectTrans and TestBackend don't perform any checks
bug
Something isn't working
tests
Tests and testbenches (not infrastructure)
#752
opened Nov 12, 2024 by
tilk
Support arbitrary signal length in New feature or request
good first issue
Good for newcomers
count_leading_zeros
enhancement
#751
opened Nov 12, 2024 by
tilk
Memories doesn't synthetise to BRAM in Quartus toolchain
bug
Something isn't working
#749
opened Nov 7, 2024 by
piotro888
Update toolchain (including GCC to 14)
infrastructure
CI, testing, etc.
#748
opened Nov 5, 2024 by
tilk
Upgrade Pyright to latest (387)
dependencies
Pull requests that update a dependency file
#746
opened Nov 5, 2024 by
tilk
Register file using synchronous memory
enhancement
New feature or request
optimization
This is *just* an optimization!
#737
opened Oct 22, 2024 by
tilk
Ordered collections
question
Further information is requested
#707
opened May 20, 2024 by
lekcyjna123
Order of announcing executed instructions
optimization
This is *just* an optimization!
#702
opened May 10, 2024 by
xThaid
Bit-vector free RF list with superscalarity
enhancement
New feature or request
good first issue
Good for newcomers
Red/green arrows in benchmark bot comments
good first issue
Good for newcomers
infrastructure
CI, testing, etc.
#672
opened Apr 19, 2024 by
tilk
Instruction Fusion
enhancement
New feature or request
nice to have
Could be useful, but not a top priority
optimization
This is *just* an optimization!
Parallelize riscv-arch-test suite
infrastructure
CI, testing, etc.
#602
opened Mar 5, 2024 by
piotro888
Skip instructions on core flush in RSes
optimization
This is *just* an optimization!
#598
opened Mar 5, 2024 by
piotro888
Remove the reduntant FIFO implementation
good first issue
Good for newcomers
nice to have
Could be useful, but not a top priority
refactor
Doesn't change functionality, but makes stuff nicer
#575
opened Jan 29, 2024 by
xThaid
Analyse support for FMADD and FMSUB
enhancement
New feature or request
microarch
Involves the processor's microarchitecture
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