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Wide FIFO #23

Merged
merged 12 commits into from
Dec 11, 2024
Merged

Wide FIFO #23

merged 12 commits into from
Dec 11, 2024

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tilk
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@tilk tilk commented Nov 30, 2024

This PR introduces a wide FIFO data structure, which allows writing and reading multiple entries in a cycle. The entries are left-aligned and the order is preserved.

TODO:

@tilk tilk added the enhancement New feature or request label Nov 30, 2024
@tilk tilk marked this pull request as ready for review December 3, 2024 20:02
@tilk tilk requested a review from lekcyjna123 December 5, 2024 09:55
@@ -0,0 +1,188 @@
from amaranth import *
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Docstrings will be welcome, so that user can check API on the docs webpage. It would be good to underline the difference between Amaranth provided shifts and rotates, and these ones. I haven't found at the start, that this are signal based shifts in contrast to constants in Amaranth lib.

def generic_shift_vec_right(
data1: Sequence[ValueLike | ValueCastable], data2: Sequence[ValueLike | ValueCastable], offset: ValueLike
) -> Sequence[Value | ValueCastable]:
shape = shape_of(data1[0])
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Shouldn't be here an assert for non-zero length of data1?

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Added.

m.submodules[f"storage{i}"] = mem

write_ports = [mem.write_port() for mem in storage]
read_ports = [mem.read_port(domain="sync", transparent_for=[port]) for mem, port in zip(storage, write_ports)]
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Is the transparency needed?

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I believe so, same as in BasicFifo. Explanation: if the FIFO is empty and a write is performed in cycle 1, then if read is called in cycle 2, it needs to return the value written in cycle 1, which is provided thanks to transparency. If you remove transparency, the test fails.

Comment on lines +265 to +268
m.d.comb += next_read_row.eq(read_row)
m.d.comb += next_read_col.eq(read_col)
m.d.sync += read_row.eq(next_read_row)
m.d.sync += read_col.eq(next_read_col)
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High surprise factor. A comment in the code will be useful.

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Thought it was a popular design pattern in HDLs. Still, I will leave a comment.

(shift_vec_right, lambda mkc: [], lambda val, offset, mkc: val[offset:] + [mkc(0)] * offset),
(
shift_vec_left,
lambda mkc: [("placeholder", mkc(0))],
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Shouldn't be mkc(1)? With 0 test is nearly the same as previous shift_vec_left.

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Will fix.

count = random.randint(1, self.write_width)
data = [const_of(random.randrange(2**self.bits), self.shape) for _ in range(self.write_width)]
await self.circ.write.call(sim, count=count, data=data)
await sim.delay(2e-9)
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Usage of 2e-9 is not very clear to me. Why that value and not 1e-9? Shouldn't we use some variable with cycle length instead?

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Because 1e-9 is used in a different testbench process. This is used to enforce execution order without synchronization primitives, which sadly are not provided (?) by Amaranth.

@tilk tilk merged commit 9eb4d17 into master Dec 11, 2024
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@tilk tilk deleted the tilk/wide-fifo branch December 11, 2024 16:25
github-actions bot pushed a commit that referenced this pull request Dec 11, 2024
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2 participants