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Merge pull request #61 from leonow32/decimal_counter
Decimal counter
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@echo off | ||
iverilog -o top.o ^ | ||
top.v ^ | ||
top_tb.v ^ | ||
double_dabble.v ^ | ||
../rotary_encoder/encoder.v ^ | ||
../synchronizer/synchronizer.v ^ | ||
../edge_detector/edge_detector.v ^ | ||
../display_multiplexed_variable/display_multiplex.v ^ | ||
../decoder_7seg/decoder_7seg.v ^ | ||
../strobe_generator/strobe_generator.v | ||
vvp top.o | ||
del top.o |
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[*] | ||
[*] GTKWave Analyzer v3.3.100 (w)1999-2019 BSI | ||
[*] Mon Dec 25 10:29:58 2023 | ||
[*] | ||
[dumpfile] "top.vcd" | ||
[dumpfile_mtime] "Mon Dec 25 10:29:37 2023" | ||
[dumpfile_size] 88325 | ||
[savefile] "top.gtkw" | ||
[timestart] 0 | ||
[size] 1920 1009 | ||
[pos] -9 -9 | ||
*-17.902624 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | ||
[treeopen] top_tb. | ||
[treeopen] top_tb.DUT. | ||
[treeopen] top_tb.DUT.DisplayMultiplex_inst. | ||
[treeopen] top_tb.DUT.Encoder_inst. | ||
[sst_width] 197 | ||
[signals_width] 201 | ||
[sst_expanded] 1 | ||
[sst_vpaned_height] 297 | ||
@28 | ||
top_tb.Reset | ||
top_tb.Clock | ||
@200 | ||
-Encoder | ||
@28 | ||
top_tb.DUT.Encoder_inst.AsyncA_i | ||
top_tb.DUT.Encoder_inst.AsyncB_i | ||
top_tb.DUT.Encoder_inst.Increment_o | ||
top_tb.DUT.Encoder_inst.Decrement_o | ||
@200 | ||
-Counter | ||
@24 | ||
top_tb.DUT.Counter[15:0] | ||
@22 | ||
top_tb.DUT.Decimal[15:0] | ||
@200 | ||
-Display | ||
@22 | ||
top_tb.DUT.DisplayMultiplex_inst.Data_i[31:0] | ||
@28 | ||
top_tb.DUT.DisplayMultiplex_inst.SwitchCathode_o | ||
@22 | ||
top_tb.DUT.DisplayMultiplex_inst.Cathodes_o[7:0] | ||
top_tb.DUT.DisplayMultiplex_inst.Segments_o[7:0] | ||
[pattern_trace] 1 | ||
[pattern_trace] 0 |
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// 231224 | ||
|
||
`default_nettype none | ||
|
||
module top #( | ||
parameter CLOCK_HZ = 25_000_000 | ||
)( | ||
input wire Clock, // Pin 20 | ||
input wire Reset, // Pin 17 | ||
input wire EncoderA_i, // Pin 68 | ||
input wire EncoderB_i, // Pin 67 | ||
output wire [7:0] Cathodes_o, // Pin 40 41 42 43 45 47 51 52 | ||
output wire [7:0] Segments_o // Pin 39 38 37 36 35 34 30 29 | ||
); | ||
|
||
// Encoder instance | ||
wire Increment; | ||
wire Decrement; | ||
|
||
Encoder Encoder_inst( | ||
.Clock(Clock), | ||
.Reset(Reset), | ||
.AsyncA_i(EncoderA_i), | ||
.AsyncB_i(EncoderB_i), | ||
.AsyncS_i(1'b1), | ||
.Increment_o(Increment), | ||
.Decrement_o(Decrement), | ||
.ButtonPress_o(), | ||
.ButtonRelease_o(), | ||
.ButtonState_o() | ||
); | ||
|
||
// Up/down counter, range 0...9999 decimal | ||
reg [15:0] Counter; | ||
|
||
always @(posedge Clock, negedge Reset) begin | ||
if(!Reset) begin | ||
Counter <= 0; | ||
end else if(Increment) begin | ||
if(Counter == 16'd9999) | ||
Counter <= 16'd0; | ||
else | ||
Counter <= Counter + 1'b1; | ||
end else if(Decrement) begin | ||
if(Counter == 16'd0) | ||
Counter <= 16'd9999; | ||
else | ||
Counter <= Counter - 1'b1; | ||
end | ||
end | ||
|
||
// Binary to BCD converter | ||
wire [15:0] Decimal; | ||
|
||
DoubleDabble #( | ||
.INPUT_BITS(16), | ||
.OUTPUT_DIGITS(4) | ||
) DoubleDabble_inst( | ||
.Binary_i(Counter), | ||
.BCD_o(Decimal) | ||
); | ||
|
||
// Display instance | ||
DisplayMultiplex #( | ||
.CLOCK_HZ(CLOCK_HZ), | ||
.SWITCH_PERIOD_US(1000), | ||
.DIGITS(8) | ||
) DisplayMultiplex_inst( | ||
.Clock(Clock), | ||
.Reset(Reset), | ||
.Data_i({Decimal, Counter}), | ||
.DecimalPoints_i(8'b00010000), | ||
.Cathodes_o(Cathodes_o), | ||
.Segments_o(Segments_o), | ||
.SwitchCathode_o() | ||
); | ||
|
||
endmodule | ||
|
||
`default_nettype wire |
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// 231224 | ||
|
||
`timescale 1ns/1ns | ||
|
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`default_nettype none | ||
module top_tb(); | ||
|
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parameter CLOCK_HZ = 1_000_000; | ||
parameter real HALF_PERIOD_NS = 1_000_000_000.0 / (2 * CLOCK_HZ); | ||
|
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// Clock generator | ||
reg Clock = 1'b1; | ||
always begin | ||
#HALF_PERIOD_NS; | ||
Clock = !Clock; | ||
end | ||
|
||
// Variables | ||
reg Reset = 0; | ||
reg AsyncA = 1; | ||
reg AsyncB = 1; | ||
integer i; | ||
|
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// Variable dump | ||
initial begin | ||
$dumpfile("top.vcd"); | ||
$dumpvars(0, top_tb); | ||
end | ||
|
||
// Instantiate device under test | ||
top #( | ||
.CLOCK_HZ(CLOCK_HZ) | ||
) DUT( | ||
.Clock(Clock), | ||
.Reset(Reset), | ||
.EncoderA_i(AsyncA), | ||
.EncoderB_i(AsyncB), | ||
.Cathodes_o(), | ||
.Segments_o() | ||
); | ||
|
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// Test sequence | ||
initial begin | ||
$timeformat(-9, 3, "ns", 10); | ||
$display("===== START ====="); | ||
|
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@(posedge Clock); | ||
Reset = 1'b1; | ||
|
||
// 10 increment events | ||
for(i=0; i<10; i=i+1) begin | ||
#10000 AsyncA = 1'b0; | ||
#10000 AsyncB = 1'b0; | ||
#10000 AsyncA = 1'b1; | ||
#10000 AsyncB = 1'b1; | ||
#20000; | ||
end | ||
|
||
// 20 decrement events | ||
for(i=0; i<20; i=i+1) begin | ||
#10000 AsyncB = 1'b0; | ||
#10000 AsyncA = 1'b0; | ||
#10000 AsyncB = 1'b1; | ||
#10000 AsyncA = 1'b1; | ||
#20000; | ||
end | ||
|
||
@(posedge Clock); | ||
|
||
$display("====== END ======"); | ||
$finish; | ||
end | ||
|
||
endmodule |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,13 @@ | ||
@echo off | ||
iverilog -o top.o ^ | ||
top.v ^ | ||
top_tb.v ^ | ||
double_dabble.v ^ | ||
../rotary_encoder/encoder.v ^ | ||
../synchronizer/synchronizer.v ^ | ||
../edge_detector/edge_detector.v ^ | ||
../display_multiplexed_variable/display_multiplex.v ^ | ||
../decoder_7seg/decoder_7seg.v ^ | ||
../strobe_generator/strobe_generator.v | ||
vvp top.o | ||
del top.o |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,65 @@ | ||
[*] | ||
[*] GTKWave Analyzer v3.3.100 (w)1999-2019 BSI | ||
[*] Mon Dec 25 10:26:31 2023 | ||
[*] | ||
[dumpfile] "top.vcd" | ||
[dumpfile_mtime] "Mon Dec 25 10:16:22 2023" | ||
[dumpfile_size] 123314 | ||
[savefile] "top.gtkw" | ||
[timestart] 0 | ||
[size] 1920 1009 | ||
[pos] -1 -1 | ||
*-18.008570 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 | ||
[treeopen] top_tb. | ||
[treeopen] top_tb.DUT. | ||
[treeopen] top_tb.DUT.DisplayMultiplex_inst. | ||
[treeopen] top_tb.DUT.DoubleDabble_inst. | ||
[treeopen] top_tb.DUT.Encoder_inst. | ||
[sst_width] 197 | ||
[signals_width] 230 | ||
[sst_expanded] 1 | ||
[sst_vpaned_height] 466 | ||
@28 | ||
top_tb.Reset | ||
top_tb.Clock | ||
@200 | ||
-Encoder | ||
@28 | ||
top_tb.DUT.Encoder_inst.AsyncA_i | ||
top_tb.DUT.Encoder_inst.AsyncB_i | ||
[color] 3 | ||
top_tb.DUT.Encoder_inst.Increment_o | ||
top_tb.DUT.Encoder_inst.Decrement_o | ||
@200 | ||
-Counter | ||
@24 | ||
top_tb.DUT.Counter[15:0] | ||
@200 | ||
-Double Dabble | ||
@22 | ||
top_tb.DUT.DoubleDabble_inst.Binary_i[15:0] | ||
@28 | ||
[color] 3 | ||
top_tb.DUT.DoubleDabble_inst.Start_i | ||
@24 | ||
top_tb.DUT.DoubleDabble_inst.Counter[3:0] | ||
@28 | ||
top_tb.DUT.DoubleDabble_inst.Busy_o | ||
[color] 3 | ||
top_tb.DUT.DoubleDabble_inst.Done_o | ||
@22 | ||
top_tb.DUT.DoubleDabble_inst.BCD[15:0] | ||
top_tb.DUT.DoubleDabble_inst.BCD_o[15:0] | ||
@200 | ||
-Display | ||
@23 | ||
top_tb.DUT.Decimal[15:0] | ||
@22 | ||
top_tb.DUT.DisplayMultiplex_inst.Data_i[31:0] | ||
@28 | ||
top_tb.DUT.DisplayMultiplex_inst.SwitchCathode_o | ||
@22 | ||
top_tb.DUT.DisplayMultiplex_inst.Cathodes_o[7:0] | ||
top_tb.DUT.DisplayMultiplex_inst.Segments_o[7:0] | ||
[pattern_trace] 1 | ||
[pattern_trace] 0 |
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