Update UART to the new version

src/main/scala/leros/uart/UARTRx.scala

@@ -27,39 +27,39 @@ class Rx(frequency: Int, baudRate: Int) extends Module {
     val channel = new UartIO()
   })
 
-  val BIT_CNT = ((frequency + baudRate / 2) / baudRate - 1).U
-  val START_CNT = ((3 * frequency / 2 + baudRate / 2) / baudRate - 1).U
+  val BIT_CNT = ((frequency + baudRate / 2) / baudRate - 1)
+  val START_CNT = ((3 * frequency / 2 + baudRate / 2) / baudRate - 2) // -2 for the falling delay
 
-  // Sync in the asynchronous RX data, reset to 1 to not start reading after a reset
-  val rxReg = RegNext(RegNext(io.rxd, 1.U), 1.U)
+  // Sync in the asynchronous RX data
+  val rxReg = RegNext(RegNext(io.rxd, 0.U), 0.U)
+  val falling = !rxReg && (RegNext(rxReg) === 1.U)
 
   val shiftReg = RegInit(0.U(8.W))
-  val cntReg = RegInit(0.U(20.W))
+  val cntReg = RegInit(BIT_CNT.U(20.W)) // have some idle time before listening
   val bitsReg = RegInit(0.U(4.W))
-  val validReg = RegInit(false.B)
+  val valReg = RegInit(false.B)
 
   when(cntReg =/= 0.U) {
     cntReg := cntReg - 1.U
-  } .elsewhen(bitsReg =/= 0.U) {
-    cntReg := BIT_CNT
-    shiftReg := rxReg ## (shiftReg >> 1)
+  }.elsewhen(bitsReg =/= 0.U) {
+    cntReg := BIT_CNT.U
+    shiftReg := Cat(rxReg, shiftReg >> 1)
     bitsReg := bitsReg - 1.U
-    // the last bit shifted in
+    // the last shifted in
     when(bitsReg === 1.U) {
-      validReg := true.B
+      valReg := true.B
     }
-  } .elsewhen(rxReg === 0.U) {
-    // wait 1.5 bits after falling edge of start
-    cntReg := START_CNT
+  }.elsewhen(falling) { // wait 1.5 bits after falling edge of start
+    cntReg := START_CNT.U
     bitsReg := 8.U
   }
 
-  when(validReg && io.channel.ready) {
-    validReg := false.B
+  when(valReg && io.channel.ready) {
+    valReg := false.B
   }
 
   io.channel.bits := shiftReg
-  io.channel.valid := validReg
+  io.channel.valid := valReg
 }
 //- end