Merge tag 'v5.10.110' into linux-5.10-mchp

This is the 5.10.110 stable release

Documentation/admin-guide/sysctl/kernel.rst

@@ -787,6 +787,7 @@ bit 1 print system memory info
 bit 2 print timer info
 bit 3 print locks info if ``CONFIG_LOCKDEP`` is on
 bit 4 print ftrace buffer
+bit 5 print all printk messages in buffer
 ===== ============================================
 
 So for example to print tasks and memory info on panic, user can::

Documentation/core-api/dma-attributes.rst

@@ -130,3 +130,11 @@ accesses to DMA buffers in both privileged "supervisor" and unprivileged
 subsystem that the buffer is fully accessible at the elevated privilege
 level (and ideally inaccessible or at least read-only at the
 lesser-privileged levels).
+
+DMA_ATTR_OVERWRITE
+------------------
+
+This is a hint to the DMA-mapping subsystem that the device is expected to
+overwrite the entire mapped size, thus the caller does not require any of the
+previous buffer contents to be preserved. This allows bounce-buffering
+implementations to optimise DMA_FROM_DEVICE transfers.

Documentation/devicetree/bindings/mtd/nand-controller.yaml

@@ -44,7 +44,7 @@ patternProperties:
  properties:
  reg:
  description:
- Contains the native Ready/Busy IDs.
+ Contains the chip-select IDs.
 
  nand-ecc-mode:
  description:
@@ -174,6 +174,6 @@ examples:
  nand-ecc-mode = "soft";
  nand-ecc-algo = "bch";
 
- /* controller specific properties */
+ /* NAND chip specific properties */
  };
  };

Documentation/devicetree/bindings/spi/spi-mxic.txt

@@ -8,11 +8,13 @@ Required properties:
 - reg: should contain 2 entries, one for the registers and one for the direct
  mapping area
 - reg-names: should contain "regs" and "dirmap"
-- interrupts: interrupt line connected to the SPI controller
 - clock-names: should contain "ps_clk", "send_clk" and "send_dly_clk"
 - clocks: should contain 3 entries for the "ps_clk", "send_clk" and
  "send_dly_clk" clocks
 
+Optional properties:
+- interrupts: interrupt line connected to the SPI controller
+
 Example:
 
  spi@43c30000 {

Documentation/process/stable-kernel-rules.rst

@@ -168,7 +168,16 @@ Trees
  - The finalized and tagged releases of all stable kernels can be found
  in separate branches per version at:
 
- https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
+ https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
+
+ - The release candidate of all stable kernel versions can be found at:
+
+ https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git/
+
+ .. warning::
+ The -stable-rc tree is a snapshot in time of the stable-queue tree and
+ will change frequently, hence will be rebased often. It should only be
+ used for testing purposes (e.g. to be consumed by CI systems).
 
 
 Review committee

Documentation/sound/hd-audio/models.rst

@@ -261,6 +261,10 @@ alc-sense-combo
 huawei-mbx-stereo
  Enable initialization verbs for Huawei MBX stereo speakers;
  might be risky, try this at your own risk
+alc298-samsung-headphone
+ Samsung laptops with ALC298
+alc256-samsung-headphone
+ Samsung laptops with ALC256
 
 ALC66x/67x/892
 ==============

Makefile

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 VERSION = 5
 PATCHLEVEL = 10
-SUBLEVEL = 109
+SUBLEVEL = 110
 EXTRAVERSION = -linux4microchip-2021.10
 NAME = Dare mighty things
 

arch/arc/kernel/process.c

@@ -43,7 +43,7 @@ SYSCALL_DEFINE0(arc_gettls)
  return task_thread_info(current)->thr_ptr;
 }
 
-SYSCALL_DEFINE3(arc_usr_cmpxchg, int *, uaddr, int, expected, int, new)
+SYSCALL_DEFINE3(arc_usr_cmpxchg, int __user *, uaddr, int, expected, int, new)
 {
  struct pt_regs *regs = current_pt_regs();
  u32 uval;

arch/arm/boot/dts/bcm2711.dtsi

@@ -433,12 +433,26 @@
  #size-cells = <0>;
  enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
 
+ /* Source for d/i-cache-line-size and d/i-cache-sets
+ * https://developer.arm.com/documentation/100095/0003
+ * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
+ * Source for d/i-cache-size
+ * https://www.raspberrypi.com/documentation/computers
+ * /processors.html#bcm2711
+ */
  cpu0: cpu@0 {
  device_type = "cpu";
  compatible = "arm,cortex-a72";
  reg = <0>;
  enable-method = "spin-table";
  cpu-release-addr = <0x0 0x000000d8>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+ next-level-cache = <&l2>;
  };
 
  cpu1: cpu@1 {
@@ -447,6 +461,13 @@
  reg = <1>;
  enable-method = "spin-table";
  cpu-release-addr = <0x0 0x000000e0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+ next-level-cache = <&l2>;
  };
 
  cpu2: cpu@2 {
@@ -455,6 +476,13 @@
  reg = <2>;
  enable-method = "spin-table";
  cpu-release-addr = <0x0 0x000000e8>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+ next-level-cache = <&l2>;
  };
 
  cpu3: cpu@3 {
@@ -463,6 +491,28 @@
  reg = <3>;
  enable-method = "spin-table";
  cpu-release-addr = <0x0 0x000000f0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
+ next-level-cache = <&l2>;
+ };
+
+ /* Source for d/i-cache-line-size and d/i-cache-sets
+ * https://developer.arm.com/documentation/100095/0003
+ * /Level-2-Memory-System/About-the-L2-memory-system?lang=en
+ * Source for d/i-cache-size
+ * https://www.raspberrypi.com/documentation/computers
+ * /processors.html#bcm2711
+ */
+ l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
+ cache-level = <2>;
  };
  };
 

arch/arm/boot/dts/bcm2837.dtsi

@@ -40,12 +40,26 @@
  #size-cells = <0>;
  enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
 
+ /* Source for d/i-cache-line-size and d/i-cache-sets
+ * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
+ * /about-the-l1-memory-system?lang=en
+ *
+ * Source for d/i-cache-size
+ * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
+ */
  cpu0: cpu@0 {
  device_type = "cpu";
  compatible = "arm,cortex-a53";
  reg = <0>;
  enable-method = "spin-table";
  cpu-release-addr = <0x0 0x000000d8>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ next-level-cache = <&l2>;
  };
 
  cpu1: cpu@1 {
@@ -54,6 +68,13 @@
  reg = <1>;
  enable-method = "spin-table";
  cpu-release-addr = <0x0 0x000000e0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ next-level-cache = <&l2>;
  };
 
  cpu2: cpu@2 {
@@ -62,6 +83,13 @@
  reg = <2>;
  enable-method = "spin-table";
  cpu-release-addr = <0x0 0x000000e8>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ next-level-cache = <&l2>;
  };
 
  cpu3: cpu@3 {
@@ -70,6 +98,27 @@
  reg = <3>;
  enable-method = "spin-table";
  cpu-release-addr = <0x0 0x000000f0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+ next-level-cache = <&l2>;
+ };
+
+ /* Source for cache-line-size + cache-sets
+ * https://developer.arm.com/documentation/ddi0500
+ * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
+ * Source for cache-size
+ * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
+ */
+ l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
+ cache-level = <2>;
  };
  };
 };

arch/arm/boot/dts/dra7-l4.dtsi

@@ -3448,8 +3448,7 @@
  ti,timer-pwm;
  };
  };
-
- target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
+ timer15_target: target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
  compatible = "ti,sysc-omap4-timer", "ti,sysc";
  reg = <0x2c000 0x4>,
  <0x2c010 0x4>;
@@ -3477,7 +3476,7 @@
  };
  };
 
- target-module@2e000 {  /* 0x4882e000, ap 19 14.0 */
+ timer16_target: target-module@2e000 { /* 0x4882e000, ap 19 14.0 */
  compatible = "ti,sysc-omap4-timer", "ti,sysc";
  reg = <0x2e000 0x4>,
  <0x2e010 0x4>;

arch/arm/boot/dts/dra7.dtsi

@@ -1093,20 +1093,20 @@
 };
 
 /* Local timers, see ARM architected timer wrap erratum i940 */
-&timer3_target {
+&timer15_target {
  ti,no-reset-on-init;
  ti,no-idle;
  timer@0 {
- assigned-clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;
+ assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
  assigned-clock-parents = <&timer_sys_clk_div>;
  };
 };
 
-&timer4_target {
+&timer16_target {
  ti,no-reset-on-init;
  ti,no-idle;
  timer@0 {
- assigned-clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;
+ assigned-clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
  assigned-clock-parents = <&timer_sys_clk_div>;
  };
 };

arch/arm/boot/dts/exynos5250-pinctrl.dtsi

@@ -260,7 +260,7 @@
  };
 
  uart3_data: uart3-data {
- samsung,pins = "gpa1-4", "gpa1-4";
+ samsung,pins = "gpa1-4", "gpa1-5";
  samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
  samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
  samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;

arch/arm/boot/dts/exynos5250-smdk5250.dts

@@ -118,6 +118,9 @@
  status = "okay";
  ddc = <&i2c_2>;
  hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
+ vdd-supply = <&ldo8_reg>;
+ vdd_osc-supply = <&ldo10_reg>;
+ vdd_pll-supply = <&ldo8_reg>;
 };
 
 &i2c_0 {

arch/arm/boot/dts/exynos5420-smdk5420.dts

@@ -124,6 +124,9 @@
  hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
  pinctrl-names = "default";
  pinctrl-0 = <&hdmi_hpd_irq>;
+ vdd-supply = <&ldo6_reg>;
+ vdd_osc-supply = <&ldo7_reg>;
+ vdd_pll-supply = <&ldo6_reg>;
 };
 
 &hsi2c_4 {

arch/arm/boot/dts/imx53-m53menlo.dts

@@ -53,6 +53,31 @@
  };
  };
 
+ lvds-decoder {
+ compatible = "ti,ds90cf364a", "lvds-decoder";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lvds_decoder_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds_decoder_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+
  panel {
  compatible = "edt,etm0700g0dh6";
  pinctrl-0 = <&pinctrl_display_gpio>;
@@ -61,7 +86,7 @@
 
  port {
  panel_in: endpoint {
- remote-endpoint = <&lvds0_out>;
+ remote-endpoint = <&lvds_decoder_out>;
  };
  };
  };
@@ -450,7 +475,7 @@
  reg = <2>;
 
  lvds0_out: endpoint {
- remote-endpoint = <&panel_in>;
+ remote-endpoint = <&lvds_decoder_in>;
  };
  };
  };