Merge pull request #3 from FlyGoat/retarget

Retarget to openhwgroup upstream

README.md

@@ -31,7 +31,7 @@ with open(data_file(my_data_file)) as f:
 ```
 
 
-The data files come from https://github.com/antmicro/cv32e40p
+The data files come from https://github.com/openhwgroup/cv32e40p
 and are imported using `git subtrees` to the directory
 [pythondata_cpu_cv32e40p/system_verilog](pythondata_cpu_cv32e40p/system_verilog).
 
@@ -104,6 +104,6 @@ pythondata-cpu-cv32e40p
 # Issues and Fixes
 
 This package is autogenerated from the sources in
-<https://github.com/antmicro/cv32e40p>
+<https://github.com/openhwgroup/cv32e40p>
 using the [pythondata-auto](https://github.com/litex-hub/pythondata-auto)
 toolset. Pull requests and issues on this pythondata repo may not be monitored.

pythondata_cpu_cv32e40p/__init__.py

@@ -1,42 +1,45 @@
 import os.path
 __dir__ = os.path.split(os.path.abspath(os.path.realpath(__file__)))[0]
 data_location = os.path.join(__dir__, "system_verilog")
-src = "https://github.com/antmicro/cv32e40p"
+src = "https://github.com/openhwgroup/cv32e40p"
 
 # Module version
-version_str = "0.0.post152"
-version_tuple = (0, 0, 152)
+version_str = "1.0.1.post1909"
+version_tuple = (1, 0, 1, 1909)
 try:
     from packaging.version import Version as V
-    pversion = V("0.0.post152")
+    pversion = V("1.0.1.post1909")
 except ImportError:
     pass
 
 # Data version info
-data_version_str = "0.0.post10"
-data_version_tuple = (0, 0, 10)
+data_version_str = "1.0.1.post1764"
+data_version_tuple = (1, 0, 1, 1764)
 try:
     from packaging.version import Version as V
-    pdata_version = V("0.0.post10")
+    pdata_version = V("1.0.1.post1764")
 except ImportError:
     pass
-data_git_hash = "087cb61a182f6bc4f757d3430865482aaff61cba"
-data_git_describe = "v0.0-10-g087cb61"
+data_git_hash = "360d272898d81806be3377193870dbf83a3ea79f"
+data_git_describe = "v1.0.1-1764-g360d272"
 data_git_msg = """\
-commit 087cb61a182f6bc4f757d3430865482aaff61cba
-Author: Piotr Binkowski <pbinkowski@antmicro.com>
-Date:   Wed May 20 14:40:57 2020 +0200
+commit 360d272898d81806be3377193870dbf83a3ea79f
+Merge: 782283a 1079a83
+Author: Davide Schiavone <davide@openhwgroup.org>
+Date:   Sat Jul 13 09:43:40 2024 +0200
 
-    disable sim tracer
+    Merge pull request #1026 from openhwgroup/dev
+    
+    merge dev into master
 
 """
 
 # Tool version info
-tool_version_str = "0.0.post142"
-tool_version_tuple = (0, 0, 142)
+tool_version_str = "0.0.post145"
+tool_version_tuple = (0, 0, 145)
 try:
     from packaging.version import Version as V
-    ptool_version = V("0.0.post142")
+    ptool_version = V("0.0.post145")
 except ImportError:
     pass
 

pythondata_cpu_cv32e40p/system_verilog/.github/ISSUE_TEMPLATE/bug.md

@@ -0,0 +1,26 @@
+# Template for Bug Issue
+
+Please use this template if the issue that you are reporting is a (potential) bug in CV32E40P Documentation, RTL, Verification environment or Tools and Build system.
+
+<br>**Note**: Please file bugs related to the CV32E40P User Manual and RTL in https://github.com/openhwgroup/cv32e40p.
+<br>**Note**: Please file bugs related to the core-v-verif verification environment in https://github.com/openhwgroup/core-v-verif instead.
+<br>**Note**: Please file bugs related to the GNU GCC compiler in https://github.com/openhwgroup/corev-gcc instead.
+<br>**Note**: Please file bugs related to the LLVM compiler in https://github.com/openhwgroup/corev-llvm-project instead.
+<br>**Note**: Please file bugs related to the binary utils and gdb in https://github.com/openhwgroup/corev-binutils-gdb instead.
+
+## Bug Title
+A clear and concise description of what the bug is.
+
+### Component
+Indicate the component in which you found a problem (and we will add the appropriate label):
+
+**Component:Doc**: For issues in the Documentation (e.g. for README.md files)
+**Component:RTL**: For issues in the RTL (e.g. for files in the rtl directory)
+**Component:Verif**: For issues in the verification environment or test cases (e.g. for behavioral code, testbench, C code, etc.)
+**Component:Tool-and-build**: For issues in the tool and build flow (e.g. Makefile, FuseSoc, etc.)
+
+### Steps to Reproduce
+Please provide:
+1. git hash
+2. Command line
+3. Logfile and/or wave-dump info (screen shots can be useful)

pythondata_cpu_cv32e40p/system_verilog/.github/ISSUE_TEMPLATE/config.yml

@@ -0,0 +1,18 @@
+blank_issues_enabled: false
+contact_links:
+  - name: Bug
+    url: https://github.com/openhwgroup/cv32e40p/issues/new?template=bug.md
+    about: For bugs in the RTL, Documentation, Verification environment or Tool and Build system.
+    labels: "Type:Bug"
+  - name: Task
+    url: https://github.com/openhwgroup/cv32e40p/issues/new?template=task.md
+    about: For any task except bug fixes.
+    labels: "Type:Task"
+  - name: Question
+    url: https://github.com/openhwgroup/cv32e40p/issues/new?template=question.md
+    about: For general questions.
+    labels: "Type:Question"
+  - name: Enhancement
+    url: https://github.com/openhwgroup/cv32e40p/issues/new?template=enhancement.md
+    about: For feature requests and enhancements.
+    labels: "Type:Enhancement"

pythondata_cpu_cv32e40p/system_verilog/.github/ISSUE_TEMPLATE/task.md

@@ -0,0 +1,17 @@
+# Template for Task Issue
+Tasks are defined, assigned and tracked as GitHub Issues. 
+
+## Task Title
+A clear and concise description of the Task. This can go in the title bar.
+
+### Task Outcome
+Provide a brief description of what is expected. If necessary point to a specification document.
+
+### Background information
+If necessary point to a specification in an outside document.
+
+### Completion Criteria
+Answer the question: how does the Assignee know they are done?
+
+### Additional context
+Add any other context about the task here.

pythondata_cpu_cv32e40p/system_verilog/.github/release.yml

@@ -0,0 +1,10 @@
+# .github/release.yml
+
+changelog:
+  exclude:
+    labels:
+      - ignore-for-release
+  categories:
+    - title: Documentation Changes
+      labels:
+        - Component:Doc

pythondata_cpu_cv32e40p/system_verilog/.github/workflows/aws.yml

@@ -0,0 +1,33 @@
+name: aws
+on:
+  push:
+    branches:
+      - 'dev'
+
+jobs:
+  aws:
+    name: AWS Pipeline (private)
+    if: ${{ (github.actor == 'davideschiavone' || github.actor == 'MikeOpenHWGroup' || github.actor == 'zarubaf') && github.event.label.name != 'Component:Doc' }}
+    runs-on: ubuntu-latest
+    # These permissions are needed to interact with GitHub's OIDC Token endpoint.
+    permissions:
+      id-token: write
+      contents: read
+    steps:
+      - name: Configure AWS Credentials
+        uses: aws-actions/configure-aws-credentials@v1
+        with:
+          role-to-assume: ${{ secrets.AWS_ROLE_TO_ASSUME }}
+          aws-region: eu-west-1
+      - name: Run AWS Pipeline
+        uses: openhwgroup/aws-codebuild-run-build@master
+        with:
+          project-name: cv32e40p
+          hide-log: true
+  skip_aws:
+    name: no AWS
+    if: ${{ (github.actor == 'davideschiavone' || github.actor == 'MikeOpenHWGroup' || github.actor == 'zarubaf') && github.event.label.name == 'Component:Doc' }}
+    runs-on: ubuntu-latest
+    steps:
+      - name: info
+        run: echo "Documentation only, skipping LEC on AWS"

pythondata_cpu_cv32e40p/system_verilog/.github/workflows/aws_cv32e40p.md

@@ -0,0 +1,27 @@
+# AWS Workflow for CV32E40P
+
+AWS is used to automate all activities which require access to the licenses provided by OpenHW Group's partners.
+
+For CV32E40P this currently means the licenses for Synopsys' Formality and Cadence's Conformal, to perform Logic Equivalence Check between a new version's candidate and a reference design (the `golden reference`).
+
+Some constraints:
+- AWS' credentials are available only in the context of the main repository. This means that an AWS job cannot be started from the context of a pull request.
+- As per license agreement, the tools can be used only by OpenHW Group's members. This means that their usage must triggered by OpenHW Group staff
+- `master` branch must always be clean (no experiments)
+
+## Proposed workflow
+
+- The project has a development branch (`dev`)
+- Each PR must target `dev`
+- Each PR triggers the `check_target` action, which verifies that target branch
+- Each PR is checked and merged by an OpenHW Group member, resulting in a commit to `dev`
+- Each push to `dev` triggers the `aws` action, which starts the AWS CodeBuild job
+- A successful run of `aws` (and therefore of the related AWS CodeBuild) results in an automatic merge of the `dev` branch to `master`
+
+## Notes, open points
+
+- What happens if `aws` fails?
+At the moment, nothing. The repository owner has to analyze the cause of the failure and decide whether to rerun the action or to revert the commit
+
+- Why not implementing an automatic revert upon failure?
+This idea could apparently make the workflow cleaner, but it could also make it much more complex. A CodeBuild job could fail for reasons which are independent from the quality of the code (e.g. licensing issues): in these cases, an autorevert would make the flow a bit more complex.

pythondata_cpu_cv32e40p/system_verilog/.github/workflows/check_target_on_pr.yml

@@ -0,0 +1,11 @@
+name: check_target
+on: [push, pull_request]
+
+jobs:
+  check_target:
+    runs-on: ubuntu-latest
+    steps:
+      - if: ${{ (github.event.pull_request.head.ref == 'dev' && github.event.pull_request.base.ref == 'master') || github.event.pull_request.base.ref == 'dev' || github.event.push.ref != 'refs/heads/master'}}
+        run: exit 0
+      - if: ${{ github.event.pull_request.base.ref != 'dev' || github.event.push.ref == 'refs/heads/master'}}
+        run: exit 1

pythondata_cpu_cv32e40p/system_verilog/.github/workflows/lint.yml

@@ -0,0 +1,39 @@
+# Copyright 2022 OpenHW Group
+# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+# Run all lint checks
+name: lint
+on: [push, pull_request]
+
+env:
+  VERIBLE_VERSION: 0.0-1149-g7eae750
+
+jobs:
+  ##################
+  # Verible Fromat #
+  ##################
+  format_verilog:
+    name: Format Verilog Sources
+    # This job runs on Linux (fixed ubuntu version)
+    runs-on: ubuntu-20.04
+    steps:
+    - uses: actions/checkout@v2
+    - uses: actions/setup-python@v2
+      with:
+        python-version: 3.9
+    - name: Install requirements
+      run: pip install -r python-requirements.txt
+    - name: Install Verible
+      run: |
+        set -e
+        mkdir -p build/verible
+        cd build/verible
+        curl -Ls -o verible.tar.gz https://github.com/google/verible/releases/download/v$VERIBLE_VERSION/verible-v$VERIBLE_VERSION-Ubuntu-18.04-bionic-x86_64.tar.gz
+        sudo mkdir -p /tools/verible && sudo chmod 777 /tools/verible
+        tar -C /tools/verible -xf verible.tar.gz --strip-components=1
+        echo "PATH=$PATH:/tools/verible/bin" >> $GITHUB_ENV
+    - name: Run Format
+      run: |
+        util/format-verible
+        util/git-diff.py --error-msg "::error ::Found differences, run util/format-verible before committing."

pythondata_cpu_cv32e40p/system_verilog/.github/workflows/merge_dev_to_master.yml

@@ -0,0 +1,24 @@
+name: Merge dev to master
+
+on:
+  workflow_run:
+    workflows: [aws]
+    types:
+      - completed
+
+jobs:
+  pull_request:
+    if: github.event.workflow_run.conclusion == 'success'
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v2
+    - name: pull-request
+      uses: repo-sync/pull-request@v2
+      with:
+        source_branch: "dev"
+        destination_branch: "master"
+        pr_title: "Automatic PR dev->master"
+        pr_body: "AWS tests passed. `dev` branch can be merged to `master`."
+        pr_reviewer: "davideschiavone"
+        pr_allow_empty: true
+        github_token: ${{ secrets.GITHUB_TOKEN }}

pythondata_cpu_cv32e40p/system_verilog/.gitignore

@@ -18,3 +18,11 @@ TAGS
 /build
 /Bender.lock
 /Bender.local
+golden_reference_design
+ref_design
+golden.src
+revised.src
+cadence_conformal
+synopsys_formality
+questa_autocheck
+reports

pythondata_cpu_cv32e40p/system_verilog/.readthedocs.yaml

@@ -0,0 +1,24 @@
+# Configuration file for ReadTheDocs, used to render the CV32E40P User Manual to
+# https://docs.openhwgroup.org/projects/cv32e40p-user-manual
+# SPDX-License-Identifier:Apache-2.0 WITH SHL-2.1
+
+version: 2
+
+build:
+  os: "ubuntu-20.04"
+  tools:
+    python: "3.9"
+
+# Build from the docs/source directory with Sphinx
+sphinx:
+  configuration: docs/source/conf.py
+
+formats:
+  - htmlzip
+  - pdf
+  - epub
+
+# Explicitly set the Python requirements
+python:
+  install:
+    - requirements: docs/requirements.txt

pythondata_cpu_cv32e40p/system_verilog/.travis.yml

@@ -1,3 +1,17 @@
+# Copyright 2020 ETH Zurich
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
 language: cpp
 # run on new infrastructure
 dist: xenial